Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 169

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
JUMPER SUMMARY
Table 12 includes only those connector blocks intended to
be populated by 2-pin option jumpers. J1-J15 and J26 are
Jumpers
J9-J7 thru -9
J10-J7 thru -9
J12-J7 thru -9
J16-J1 thru -3
J17-J1 to -2
J17-J3 thru -6
J18-J1 thru -3
J19-J1 thru -6
J20-J1 thru -3
J21-J1 thru -6
J22-J1 thru -4
J23-J1 thru -3
J24-J1 thru -4
J25-J1 thru - 5 and J25X 1 to 2 and 3 to 4: (E)SCC last on IACK chain,
J28-J1 thru -6
J29-J1 thru -4
Installed
7 to 8: 80186 SYSCLK is IUSC /RxC
7 to 9: 80186 SYSCLK is IUSC /TxC
7 to 8: 80186 SYSCLK is MUSC (USC A) /RxC
7 to 9: 80186 SYSCLK is MUSC (USC A) /TxC
7 to 8: 80186 SYSCLK is USC B /RxC
7 to 9: 80186 SYSCLK is USC B /TxC
1 to 2: J3, J4 TxD driven when RTS
2 to 3: J3, J4 TxD, RTS driven full-time
Unbalanced DCD- on J3 or J4
3 to 5 and 4 to 6: CTS+ on J4-J2
3 to 4 and 5 to 6: CTS- on J3 or J4
1 to 2: 2764, 27128, 27256 EPROMs
2 to 3: 27512 EPROMs
1 to 2 and 4 to 5: 128K x 8 SRAMs
2 to 3 and 5 to 6: 32K x 8 SRAMs
1 to 2: U2 contains 80C30 or 80230
2 to 3: U2 contains 85C30 or 85230
1 to 2 and 4 to 5: U2 contains 80C30 or 80230
2 to 3 and 5 to 6: U2 contains 85C30 or 85230
1 to 2: MUSC (USC A) RxREQ on DMA 0
1 to 3: MUSC (USC A) RxREQ on DMA 1
2 to 4: MUSC (USC A) TxREQ on DMA 0
3 to 4: MUSC (USC A) TxREQ on DMA 1
1 to 2: (E)SCC B RxRQ on DMA 0
2 to 3: (E)SCC B Wait function
1 to 2: clipped SCC B TxREQ on DMA 1
1 to 3: direct ESCC B TxREQ on DMA 1
3 to 4: /DTR output from ESCC B
MUSC second to last
J25X to 2 and 3 to 4: (E)SCC last, USC 2nd to last
1 to 2: 80186 SYSCLK is (E)SCC PCLK
3 to 4: 80186 SYSCLK is ISCC PCLK
5 to 6: 80186 SYSCLK is IUSC CLK
1 to 2: USC B RxREQ on DMA 0
1 to 3: USC B RxREQ on DMA 1
2 to 4: USC B TxREQ on DMA 0
3 to 4: USC B TxREQ on DMA 1
2 to 3 and 4 to 5: (E)SCC first on IACK chain
Table 12. Two-Pin Option Jumpers
actual connectors meant for use with cables, jumper wires,
or wire-wrapped connections.
The Zilog Datacom Family with the 80186 CPU
Open
8: Something else on /RxC, or N/C
9: Something else on /TxC, or N/C
8: Something else on /RxC, or N/C
9: Something else on /TxC, or N/C
8: Something else on /RxC, or N/C
9: Something else on /TxC, or N/C
Must install one or the other
Differential DCD+, DCD- on J3
Differential CTS+, CTS- on J3
Must install one or the other
Must install one way or the other
Must install one way or the other
Must install one way or the other
1: MUSC (USC A) Rx no DMA
4: MUSC (USC A) Tx no DMA
(E)SCC B neither Rx DMA
nor Wait
(E)SCC B neither Tx DMA
nor /DTR
Must be one of these three ways
Connect some other clock to 2, 4, or 6
1: USC B Rx no DMA
4: USC B Tx no DMA
Application Note
9-15
8