Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 25

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
3.4 DATA ENCODING/DECODING
The ISCC provides four different data encoding methods,
selected by bits D6 and D5 in WR10. An example of these
four encoding methods is shown in Figure 3-3. Any
encoding method may be used in any X1 mode in the
In NRZ, encoding a “1” is represented by a HIGH level and
a “0” is represented by a LOW level. In this encoding meth-
od, only a minimal amount of clocking information is avail-
able in the data stream in the form of transitions on bit-cell
boundaries. In an arbitrary data pattern, this may not be suf-
ficient to generate a clock for the data from the data itself.
In NRZI, encoding a “1” is represented by no change in the
level and a “0” is represented by a change in the level. As
in NRZ, only a minimal amount of clocking information is
available in the data stream, in the form of transitions on
bit cell boundaries. In an arbitrary data pattern this may not
be sufficient to generate a clock for the data from the data
itself. In the case of SDLC, where the number of consecu-
tive “1s” in the data stream is limited, a minimum number
of transitions to generate a clock are guaranteed.
In FM1 encoding, also known as biphase mark, a transition
is present on every bit cell boundary, and an addition tran-
sition may be present in the middle of the bit cell. In FM1 a
“0” is sent as no transition in the center of the bit cell and a
“1” is sent as a transition in the center of the bit cell. FM1
encoded data contains sufficient information to recover a
clock from the data.
(Biphase Space)
MANCHESTER
(Biphase Mark)
DATA
NRZI
NRZ
FM1
FM0
1
1
Figure 3-3. Data Encoding Methods
0
0
1
ISCC, asynchronous or synchronous. The data encoding
selected is active even though the transmitter or receiver
may be idling or disabled. The data encoding methods are
shown in Figure 3-3.
In FM0 encoding, also known as biphase space, a transi-
tion is present on every bit cell boundary and an additional
transition may be present in the middle of the bit cell. In
FM0, a “1” is sent as no transition in the center of the bit
cell and a “0” is sent as a transition in the center of the bit
cell. FM0 encoded data contains sufficient information to
recover a clock from the data.
Manchester encoding, which is not directly supported, al-
ways produces a transition at the center of the bit cell. If
the transition is Low to High, the bit is “0.” If the transition
is High to Low, the bit is “1.” ISCC can be used to decode
Manchester (biphase level) data by using the DPLL in the
FM mode and programming the receiver for NRZ data.
(See section 3.5.3.)
The data encoding method should be selected in the initial-
ization procedure before the transmitter and receiver are
enabled, but no other restrictions apply. Note, in Figure 3-
3, that in NRZ and NRZI the receiver samples the data only
on one edge. However, in FM1 and FM0 the receiver sam-
ples the data on both edges. Also, as shown in Figure 6-4,
the transmitter defines bit cell boundaries by one edge in
all cases and uses the other edge in FM1 and FM0 to cre-
ate the mid-bit transition.
0
ISCC™ DMA and Ancillary Support Circuitry
Z16C35ISCC™ User’s Manual
Bit Cell Level:
High = 1
Low = 0
No Change = 1
Change = 0
3-5
3