MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 118

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
7.11.4
Serial communications status register (SCSR)
State
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
on reset
SCI status (SCSR)
$0010
TDRE
TC
RDRF
IDLE
OR
NF
FE
1100 000u
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
TDRE — Transmit data register empty flag
This bit is set when the contents of the transmit data register are transferred to the serial shift
register. New data will not be transmitted unless the SCSR register is read before writing to the
transmit data register to clear the TDRE flag.
If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial
communications data register will overwrite the previous value. The TDRE bit is cleared by
accessing the serial communications status register (with TDRE set) followed by writing to the
serial communications data register.
7
TC — Transmit complete flag
This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data
in shift register, no preamble, no break). When TC is set the serial line will go idle (continuous
MARK). The TC bit is cleared by accessing the serial communications status register (with TC set)
followed by writing to the serial communications data register. It does not inhibit the transmitter
function in any way.
RDRF — Receive data register full flag
This bit is set when the contents of the receiver serial shift register are transferred to the receiver
data register.
If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as
appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications
status register is accessed (with RDRF set) followed by a read of the serial communications data
register.
IDLE — Idle line detected flag
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive ‘1’s). This bit will not be set by the idle line condition when the RWU bit is set. This
allows a receiver that is not in the wake-up mode to detect the end of a message, detect the
preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by
accessing the serial communications status register (with IDLE set) followed by a read of the serial
communications data register. Once cleared, IDLE will not be set again until after RDRF has been
set, (i.e. until after the line has been active and becomes idle again).
SERIAL COMMUNICATIONS INTERFACE
MC68HC05X16
For More Information On This Product,
Rev. 1
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