MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 144

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10
10.2.3.1
Note:
INTP, INTN — External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ and WOI pins are sensitive to as shown
in
external reset. Therefore the device is initialised with negative edge and low level sensitivity.
Interrupt sensitivity options selected by INTP and INTN of the miscellaneous register apply to
external interrupt signal, EI. EI is an OR function of all enabled WOI pins (port B and NWOI) and
of the inverted value of the IRQ pin. When one WOI pin is high, it masks any subsequent edge or
level on any other EI pin (IRQ, port B or NWOI).
INTE — External interrupt enable
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 10-3
is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is
possible to change the external interrupt options only while the I-bit is set. Any attempt to change
the external interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is
pending, it will automatically be cleared when selecting a different interrupt option.
Table
1 (set)
0 (clear) –
Miscellaneous
10-3. Both bits can be written to only while the I-bit is set, and are cleared by power-on or
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in
describes the various triggering options available for the IRQ and WOI pins, however it
INTP
0
0
1
1
Miscellaneous register
–
INTN
Freescale Semiconductor, Inc.
0
1
0
1
External interrupt (IRQ) and wired-OR interrupt (WOI) enabled.
External interrupt (IRQ) and wired-OR interrupt (WOI) disabled.
For More Information On This Product,
Negative edge and low level
sensitive
Negative edge only
Positive edge only
Positive and negative edge
sensitive
Section
Address bit 7
$000C POR INTP INTN INTE
Table 10-3 IRQ and WOI sensitivity
IRQ sensitivity
RESETS AND INTERRUPTS
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3.8.
bit 6
bit 5
Positive edge and high level
sensitive
Positive edge only
Negative edge only
Positive and negative edge
sensitive
bit 4
WOI interrupt sensitivity
bit 3
SFA
bit 2
SFB
bit 1
SM WDOG u001 000u
MC68HC05X16
bit 0
on reset
State
Rev. 1