MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 30

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

2
2.2
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.2.1
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off (providing the MCAN is ‘asleep’, see
processing including timer, serial communications interface and the A/D converter (see flow chart
in
interrupt or by the detection of a reset (logic low on RESET pin or a power-on reset.
The STOP instruction can be executed (i.e. the oscillator can be turned off) only when the MCAN
module is in SLEEP mode. See
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
Section
while exiting STOP mode (see
All other registers and memory remain unaltered and all input/output lines remain unchanged. This
continues until a MCAN interrupt, wired-OR interrupt, external interrupt (IRQ) or reset is sensed,
at which time the internal oscillator is turned on. The interrupt or reset causes the program counter
to vector to the corresponding locations ($3FFA, B and $3FFE, F respectively).
When leaving STOP mode, a t
stabilise before releasing CPU operation. This delay is selectable via a mask option to be either 16
or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or by
fetching the reset vector, if reset wakes it up.
Note:
The following list summarizes the effect of STOP mode on the modules of the MC68HC05X16.
Figure
– The watchdog timer is reset; see
– The EEPROM acts as read-only memory (ROM); see
– All SCI activity stops; see
– The timer stops counting; see
– The PLM outputs remain at current levels; see
– The A/D converter is disabled; see
– The I-bit in the CCR is cleared
11.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count
2-4). The MCU will wake up from STOP mode only by receipt of an MCAN external
If t
used to avoid problems with oscillator stability while the device is in STOP mode.
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
PORL
Low power modes
STOP mode
is selected to be 16 cycles, it is recommended that an external clock signal is
Freescale Semiconductor, Inc.
MODES OF OPERATION AND PIN DESCRIPTIONS
For More Information On This Product,
PORL
Section
Section
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internal cycles delay is provided to give the oscillator time to
Section 7.13
2.2.3).
5.5.
Section 6.6
Section 10.1.4.1
Section 9.3
Section 8.3
Section 3.6
Section
5.5) halting all internal
MC68HC05X16
Rev. 1