MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 138

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10
The watchdog system can be automatically enabled, following power-on or external reset, via a
mask option (see
the miscellaneous register at $000C (see
cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In
addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this
bit clears the counter to its initial value and prevents a watchdog timeout.
WDOG — Watchdog enable/disable
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
The divide-by-7 watchdog counter will generate a main reset of the chip when it reaches its final
state; seven clocks are necessary to bring the watchdog counter from its clear state to its final
state. This reset appears after time t
counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with
a period less than t
The reset generated by the watchdog system is apparent at the RESET pin (see
RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’
for a minimum of t
f
osc
f
osc
Main CPU
/32
/2
clock
1 (set)
0 (clear) –
prescaler
4
–
Section
DOGL
DOG
Freescale Semiconductor, Inc.
running counter)
bit has no effect.
Watchdog enabled and counter cleared.
The watchdog cannot be disabled by software; writing a zero to this
(Bit 7 of free
, the RESET pin is released.
.
WDOG bit
Figure 10-3 Watchdog system block diagram
For More Information On This Product,
1.2), or it can be enabled by software by writing a ‘1’ to the WDOG bit in
256
RESETS AND INTERRUPTS
Go to: www.freescale.com
DOG
Control logic
7 watchdog
counter
since the last clear or since the enable of the watchdog
Section
10.1.2). Once enabled, the watchdog system
R
S
Schmitt
trigger
Latch
protection
Power-on
Input
Figure
MC68HC05X16
10-3). The
Reset
pin
Rev. 1