MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 50

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

3
EE1P – EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
of the options register.
When this bit is set (erased), the protection will remain until the next power-on or external reset.
EE1P can only be written to ‘0’ when the ELAT bit in the EEPROM control register is set.
SEC – Security bit
This high security bit allows the user to secure the EEPROM data from external accesses. When
the SEC bit is at ‘0’, the EEPROM contents are secured by preventing any entry to test mode. The
only way to erase the SEC bit to ‘1’ externally is to enter bootstrap mode, at which time the entire
EEPROM contents will be erased. When the SEC bit is changed, its new value will have no effect
until the next external or power-on reset.
3.6
When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1
high voltage charge pump generator is automatically disabled.
3.7
The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in
normal operating mode. The charge pump is not affected by WAIT mode, therefore it is possible to
wait the t
Under normal operating conditions, the charge pump generator is driven by the internal CPU
clocks. When the operating frequency is low, e.g. during slow mode (see
WAIT mode, the clocking should be done by the internal A/D RC oscillator. The RC oscillator is
enabled by setting the ADRC bit of the A/D status/control register at $0009.
1 (set)
0 (clear) –
ERA1
EEPROM during STOP mode
EEPROM during WAIT mode
erase time or t
–
Freescale Semiconductor, Inc.
can be accessed for any read, erase or programming operations
program a location will be unsuccessful
Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM
Part 2 of the EEPROM array is protected; any attempt to erase or
For More Information On This Product,
PROG1
MEMORY AND REGISTERS
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programming time in WAIT mode.
Figure
MC68HC05X16
3.8) or during
Rev. 1