MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 136

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled,
10.1.1
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (t
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time t
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage. This may be accomplished by connecting an external RC
circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be great
enough to allow the oscillator circuit to stabilize.
During power-on reset, the RESET pin is driven low during a t
defined by a user specified mask option to be either 16 cycles or 4064 cycles (see
A software distinction between a power-on reset and an external reset can be made using the POR
bit in the miscellaneous register (see
10.1.2
POR — Power-on reset bit
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
Note:
0=watchdog disabled.
1 (set)
0 (clear) –
Miscellaneous
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in
Power-on reset
Miscellaneous register
–
Freescale Semiconductor, Inc.
A power-on reset has occurred.
No power-on reset has occurred.
For More Information On This Product,
Section
Address bit 7
$000C POR
RESETS AND INTERRUPTS
Go to: www.freescale.com
3.8.
Section
(1)
INTP INTN INTE
bit 6
10.1.2).
bit 5
bit 4
PORL
bit 3
SFA
delay start-up sequence. t
bit 2
SFB
PORL
bit 1
SM WDOG
PORL
) from when the
Section
MC68HC05X16
bit 0
has elapsed.
(2)
1.2).
u001 000u
on reset
PORL
State
Rev. 1
is