MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 69

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MCAN command (CCOM) $0020
RIE — Receive interrupt enable
RR — Reset request
When the MCAN detects that RR has been set it aborts the current transmission or reception of a
message and enters the reset state. A reset request may be generated by either an external reset
or by the CPU or by the MCAN. The RR bit can be cleared only by the CPU. After the RR bit has
been cleared, the MCAN will start normal operation in one of two ways. If RR was generated by
an external reset or by the CPU, then the MCAN starts normal operation after the first occurrence
of 11 recessive bits. If, however, the RR was generated by the MCAN due to the BS bit being set
(see
normal operation.
A reset request should not be generated by the CPU during a message transmission. Ensure that
a message is not being transmitted as follows:
Note that a CPU-generated reset request does not change the values in the transmit and receive
error counters.
Note:
5.3.2
This is a write only register; a read of this location will always return the value $FF.
This register may be written only when the RR bit in CCNTRL is clear.
Do not use read-modify-write instructions on this register (e.g. BSET, BCLR).
MC68HC05X16
Section
1 (set)
0 (clear) –
1 (set)
0 (clear) –
The following registers may only be accessed when reset request = present: CACC,
CACM, CBT0, CBT1, and COCNTRL.
5.3.3) the MCAN waits for 128 occurrences of 11 recessive bits before starting
if TCS in CSTAT is clear – set AT in CCOM (use STA or STX), read CSTAT.
if TS in CSTAT is set – wait until TS is clear.
MCAN command register (CCOM)
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–
–
Address
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message has been received free of errors.
Enabled – The CPU will get an interrupt request whenever a
Disabled – The CPU will get no receive interrupt request.
Present – MCAN will be reset.
Absent – MCAN will operate normally.
bit 7
RX0
MOTOROLA CAN MODULE (MCAN)
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bit 6
RX1
COMPSEL
bit 5
SLEEP COS
bit 4
bit 3
RRB
bit 2
bit 1
AT
bit 0
TR
External reset 00u0 0000
RR bit set
condition
Reset
00u0 0000
on reset
State
5-7
5