MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 79

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Calculation of the bit time
Note:
i.e. in terms of t
These boundary conditions result in minimum bit times of 5 t
three samples per bit.
MC68HC05X16
TSEG13 TSEG12 TSEG11 TSEG10
0
0
0
1
.
.
TSEG2 must be at least 2 t
samples per bit mode is selected then TSEG2 must be at least 3 t
TSEG1 must be at least as long as TSEG2.
The synchronization jump width (SJW) may not exceed TSEG2, and must be at least
t
and
or
SCL
0
0
0
1
.
.
Freescale Semiconductor, Inc.
SCL
shorter than TSEG1 to allow for physical propagation delays.
:
0
1
1
1
.
.
For More Information On This Product,
BIT_TIME
SYNC_SEG = 1
1
0
1
1
MOTOROLA CAN MODULE (MCAN)
.
.
Go to: www.freescale.com
TSEG1
TSEG1 TSEG2
TSEG2
TSEG2
TSEG2
Table 5-3 Time segment values
Time segment 1
16 t
=
2 t
3 t
4 t
SCL
SCL
SCL
SCL
SYNC_SEG
SCL
SJW + 1
SJW
2
3
.
.
cycles
cycles
cycles
, i.e. the configuration bits must not be 000. (If three
cycles
(SAMP = 0)
(SAMP = 1)
+
TSEG1
TSEG22 TSEG21 TSEG20
0
1
.
.
SCL
+
TSEG2
, for one sample, and 7 t
0
1
.
.
1
1
.
.
SCL
.)
Time segment 2
2 t
8 t
SCL
SCL
.
.
cycles
cycles
SCL
5-17
, for
5