MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 68

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

5
5.3.1
This register may be read or written to by the MCU; only the RR bit is affected by the MCAN.
MODE — Undefined mode
This bit must never be set by the CPU as this would result in the transmit and receive buffers being
mapped out of memory. The bit is cleared on reset, and should be left in this state for normal
operation.
SPD — Speed mode
OIE — Overrun interrupt enable
EIE — Error interrupt enable
TIE — Transmit interrupt enable
MCAN control (CCNTRL)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
MCAN control register (CCNTRL)
–
–
–
–
Freescale Semiconductor, Inc.
Address
from ‘dominant’ to ‘recessive’ will be used for resynchronization.
resynchronization.
Overrun Status bit gets set.
status or bus status bits in the CSTAT register change.
message has been successfully transmitted, or when the transmit
buffer is accessible again following an ABORT command.
Slow – Bus line transitions from both ‘recessive’ to ‘dominant’ and
Fast – Only transitions from ‘recessive’ to ‘dominant’ will be used for
Enabled – The CPU will get an interrupt request whenever the
Disabled – The CPU will get no overrun interrupt request.
Enabled – The CPU will get an interrupt request whenever the error
Disabled – The CPU will get no error interrupt request.
Enabled – The CPU will get an interrupt request whenever a
Disabled – The CPU will get no transmit interrupt request.
$0020 MODE SPD
For More Information On This Product,
bit 7
MOTOROLA CAN MODULE (MCAN)
Go to: www.freescale.com
bit 6
bit 5
bit 4
OIE
bit 3
EIE
bit 2
TIE
bit 1
RIE
bit 0
RR
External reset 0u - u uuu1
RR bit set
condition
Reset
MC68HC05X16
0u - u uuu1
on reset
State
Rev. 1