MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 94

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6
6.2.2
The timer status register ($13) contains the status bits corresponding to the timer interrupt
conditions – ICF1, OCF1, TOF, ICF2 and OCF2.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
ICF1 — Input capture flag 1
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading
the TSR and then the input capture low register 1 ($15).
OCF1 — Output compare flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then the output compare 1 low register ($17).
TOF — Timer overflow status flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($19).
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
Timer status (TSR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 The timer status register is read or written when TOF is set, and
2 The LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Timer status register (TSR)
–
–
–
Freescale Semiconductor, Inc.
A valid input capture has occurred.
No input capture has occurred.
A valid output compare has occurred.
No output compare has occurred.
Timer overflow has occurred.
No timer overflow has occurred.
For More Information On This Product,
Address
$0013
Go to: www.freescale.com
PROGRAMMABLE TIMER
ICF1
bit 7
OCF1
bit 6
TOF
bit 5
ICF2
bit 4
OCF2
bit 3
bit 2
bit 1
MC68HC05X16
bit 0
Undefined
on reset
State
Rev. 1