MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 53

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
3.8
POR — Power-on reset bit (see
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
INTP, INTN — External interrupt sensitivity options (see
These two bits allow the user to select which edge the IRQ pin and WOI will be sensitive to (see
Table
external reset, thus the device is initialised with negative edge and low level sensitivity.
INTE — External interrupt enable (see
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
SFA — Slow or fast mode selection for PLMA (see
MC68HC05X16
3-4). Both bits can be written to only while the I-bit is set, and are cleared by power-on or
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Miscellaneous
INTP
0
0
1
1
Freescale Semiconductor, Inc.
Miscellaneous register
–
–
–
INTN
0
1
0
1
For More Information On This Product,
A power-on reset has occurred.
No power-on reset has occurred.
External interrupt function (IRQ) enabled.
External interrupt function (IRQ) disabled.
Slow mode PLMA (4096 x timer clock period).
Fast mode PLMA (256 x timer clock period).
Negative edge and low level sensitive
Negative edge only
Positive edge only
Positive and negative edge sensitive
Address
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$000C POR
Table 3-4 IRQ and WOI sensitivity
MEMORY AND REGISTERS
Section
IRQ sensitivity
bit 7
(1)
Section
10.1)
INTP
bit 6
INTN
10.2)
bit 5
Section
Positive edge and high level sensitive
Positive edge only
Negative edge only
Positive and negative edge sensitive
INTE
bit 4
Section
WOI interrupt options
8.1)
bit 3
SFA
10.2)
SFB
bit 2
bit 1
SM WDOG
bit 0
(2)
u001 000u
on reset
State
3-11
3