CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 129

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 5-12. Host and SAR-Shared Memory Data Structures for Scatter Method
5.4.3 Free Buffer Queues
28236-DSH-001-B
The free buffer queue structure consists of a free buffer queue base table, two
base address registers, RSM_FQBASE(FBQ0_BASE and FBQ1_BASE), and the
corresponding free buffer queues.
BFR0 and BFR1. These fields identify the free buffer queues that have been
assigned to this channel by the host during initialization of the VCC table entry.
BFR0 contains the BOM free buffer queue number, and BFR1 contains the COM
free buffer queue number. Typically, the BFR0 number is for free buffer queues
0–15, and the BFR1 number is for free buffer queues 16–31.
queues 0–15, and Bank 1 contains free buffer queues 16–31.
corresponding BFRx buffer number is used as an index to the appropriate free
buffer queue base table entry.
FBQ1_BASE). The reassembly coprocessor calculates the address of the first
entry for any of the 32 free buffer queues as follows:
sequentially read by the SAR. The reassembly coprocessor calculates the index
for each sequential read as follows:
READ index pointer, and is continually updated with each read of that queue.
(BD_PNTR) and a pointer to a data buffer (BUFFER_PNTR); when the free
buffer queue entry is read, it returns those pointers.
The reassembly VCC table entry for any channel contains two 5-bit fields:
The free buffer queue is configured in two banks. Bank 0 contains free buffer
The user can set BFR0 = BFR1 to disable this two-tier buffer structure.
Depending on the type of arriving cell (whether BOM or COM), the
The base addresses for these banks are in RSM_FQBASE(FBQ0_BASE and
Each of the 32 free buffer queues is a circular queue whose entries are
The READ field in the base table entry for any free buffer queue is the current
Each free buffer queue entry contains a pointer to a buffer descriptor
Buffer Descriptors
Cell buffers
HOST
Mindspeed Technologies
FBQx_BASE
(index of first entry for the queue)
(size of each free buffer queue entry)]
+
[(size of each free buffer queue) BFRx MOD 16]
(Inside the CN8236)
Free Buffer Queues
Free Buffer Queue
SAR-Shared
Base Table
™
+
[(READ index pointer)
5.0 Reassembly Coprocessor
5.4 Buffer Management
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