CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 330

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

14.0 CN8236 Registers
14.4 Scheduler Registers
0xa8
The SCH_SIZE register sets the size of the schedule table in schedule slots and the period of a schedule slot in
system clocks.
14-14
31–16
15–14
13–0
Bit
Bit
8
7
6
5
4
3
2
1
0
—
Schedule Size Register (SCH_SIZE)
Field
Field
Size
Size
16
14
1
1
1
1
1
1
1
1
1
2
Reserved
TUN_ENA_10
GFC10
Reserved
TUN_ENA_9
GFC9
Reserved
TUN_ENA_8
GFC8
TBL_SIZE[15:0]
Reserved
SLOT_PER[13:0]
Name
Name
Mindspeed Technologies
Program and read as 0.
Enable tunnel on global priority pointer 10.
Enable GFC on global priority pointer 10.
Program and read as 0.
Enable tunnel on global priority pointer 9.
Enable GFC on global priority pointer 9.
Program and read as 0.
Enable tunnel on global priority pointer 8.
Enable GFC on global priority pointer 8.
Size of schedule table in schedule slots.
Program and read as 0.
Number of system clocks per schedule slot. The value written to the
register should be (SLOT_PER – 1). Minimum bound for SLOT_PER break
value = 70.
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
Description
28236-DSH-001-B
CN8236