CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 268

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

10.0 Local Processor Interface
10.3 Bus Cycle Descriptions
10.3.5 Quad Write Burst, No Wait States
Figure 10-6. Local Processor Quad Write, No Wait States
10-10
LADDR[18:2]
LDATA[31:0]
PADDR[1:0]
LADDR[1:0]
RAMMODE
PBSEL[1:0]
MWE*[3:0]
MCS*[3:0]
PBLAST*
SYSCLK
PBE[3:0]
PDAEN*
PWAIT*
D[31:0]
PRDY*
A[20:4]
PWNR
DT/R*
MOE*
PCS*
PAS*
1.
Address
Cycle
ta
0000
00
01
1
In
RAMMODE is logic low, selecting by_8 or by_4 RAM mode. Here PBE[3:0]* is
latched on cycle 1, indicating that the write is active on all bytes, and the
MWE*[3:0] outputs are active as write strobes while MWR* is not used. The
SAR-shared memory word select addresses, LADDR[1:0], are incremented
automatically by the CN8236 on each successive write cycle. Although the i960
architecture has the limitation that a quad word transfer must start on a quad word
boundary, the CN8236 does not have that limitation. Thus, the PADDR[1:0] bits
can be any value and are incremented as long as the burst transfer proceeds.
2.
Figure
Arbitration
Cycle
tarb
Mindspeed Technologies
10-6, a quad burst write access to 0-wait-state memory is illustrated.
2
3.
Bus
Recovery
Cycle
tbr
F
3
4.
Address
Address
Data
Cycle
00
D0
td
D0
0
ATM ServiceSAR Plus with xBR Traffic Management
4
F
5.
Data1
Cycle
td
1011
™
D1
0
01
D1
5
F
6. Data2
td
Cycle
0
D2
10
6
D2
F
7.
Data3
Cycle
td
28236-DSH-001-B
0
D3
11
7
D3
F
CN8236
8236_066