CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 285

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
11.7 Byte Swapping of Control Structures
Two control bits in the PCI configuration space are used to configure byte
swapping, in order to align with various big and little endian host system
requirements.
Configuration register. When SLAVE_SWAP is set to a logic high, the slave
interface swaps the bytes of a slave write or read access. The default setting for
this bit is logic low.
PCI Configuration register. When MSTR_CTRL_SWAP is set to a logic high, the
control structures that the SAR writes are written with bytes swapped. The default
setting for this bit is logic low.
11.8 Power Management
Power Management, as a defined class of functions, consists of mechanisms in
software and hardware to minimize system power consumption, manage system
thermal limits, and maximize system battery life. The CN8236 supports Power
Management on the PCI bus according to the PCI Bus Power Management
Interface Specification, Revision 1.0.
savings. The CN8236 device supports the two mandatory power states, D0 and
D3, of the PCI Bus Power Management Interface Specification. D0 is the
maximum powered state (on) and D3 is the minimum powered state (off). When
in the D3 state, SYSCLK is turned off.
space and PCI registers concerned with implementing the Power Management
functions.
bit 2 of the EEPROM (Disable Capability register), which sets bit 20 of the PCI
Status register to a logic low. See the PCI Bus Power Management Interface
Specification, Revision 1.0, for specific information on the functions involved in
Power Management.
The SLAVE_SWAP control bit is bit 29 of address offset 0x40 in the PCI
The MSTR_CTRL_SWAP control bit is bit 30 of address offset 0x40 in the
The HRST* pin made active causes both of these bits to be logic low.
Power management states are defined as varying, distinct levels of power
Refer to
Power Management is enabled by default. This capability can be disabled via
Mindspeed Technologies
Section 14.7
for the detailed information on the PCI Configuration
™
11.7 Byte Swapping of Control Structures
11.0 PCI Bus Interface
11-7