CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 40
CN8236EBGB
Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236EBGB.pdf
(443 pages)
Specifications of CN8236EBGB
Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
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2.0 Architecture Overview
2.2 High Performance Host Architecture with Buffer Isolation
2.2.3 Buffer Isolation Utilizing Descriptor-Based Buffer Chaining
Figure 2-4. Reassembly Buffer Isolation—Data Buffers Separated from Descriptors
2-6
LEGEND:
Data Buffers
2
Associations (Pointing Function)
Data Writes
Host Actions
SAR Actions
1
3
The CN8236 uses buffer structures for reassembly and segmentation. The buffer
structures maximize the flexibility of the system architecture by isolating the data
buffers from the mechanisms that handle buffer allocation and linking. This
allows the data buffers to contain only payload data, no control fields or other
user fields. The user can store the data buffers separately from the buffer
descriptors and implement a minimum data copy architecture.
chained together and manipulated by the ServiceSAR.
Figure 2-4
1.
2.
3.
4.
The host creates a link between a reassembly data buffer and a buffer
descriptor by writing in the buffer descriptor entry, a pointer to the data
buffer.
The host then formats a free buffer queue entry, which includes pointers to
both the data buffer and buffer descriptor, and writes this message to the
free buffer queue.
The reassembly coprocessor reads this free buffer queue entry and uses the
pointer to the reassembly data buffer as the memory location to write the
PDU being reassembled.
As reassembly of that PDU progresses, the reassembly coprocessor chains
together the necessary number of additional buffer descriptors (and thus
their associated reassembly data buffers) to complete reassembly of the
PDU.
Mindspeed Technologies
(Write)
Host (or optionally Local) Memory
illustrates how reassembly data buffers and buffer descriptors are
RSM Buffer
Descriptors
1
2
3
ATM ServiceSAR Plus with xBR Traffic Management
(SAR
Links
Buffer
Descriptors
for the
PDU.)
™
PCI
(Write)
(Write)
RSM Coprocessor
Free Buffer
Queues
(32)
(Read)
28236-DSH-001-B
RSM Memory
CN8236
CN8236
8236_004
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