CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 318

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

14.0 CN8236 Registers
14.1 Control and Status Registers
Register Terminology
Table 14-2. CN8236 Control and Status Registers (1 of 2)
14-2
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1c
0x20
0x24–0x7c
0x80
0x84
0x88
0x8c
0x90
0x94–0x9c
0xa0
0xa4
0xa8
0xac
0xb0
0xb4
0xb8
0xbc
0xc0
0xc4
0xc8–0xeC
0xf0
0xf4
0xf8
0xfC
0x100
Address
CLOCK
ALARM1
Reserved
SYS_STAT
Reserved
CONFIG0
CONFIG1
INT_DELAY
AALx_CTRL
Reserved
SEG_CTRL
SEG_VBASE
SEG_PMBASE
SEG_TXBASE
SEG_TAGBASE
Reserved
SCH_PRI
SCH_PRI_2
SCH_SIZE
SCH_CTRL
SCH_ABR_MAX
SCH_ABR_CON
SCH_ABRBASE
SCH_CNG
PCR_QUE_INT01
PCR_QUE_INT23
Reserved
RSM_CTRL0
RSM_CTRL1
RSM_FQBASE
RSM_FQCTRL
RSM_TBASE
Name
Mindspeed Technologies
R/W
R/W
—
R/O
—
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
—
R/WB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
Type
Real Time Clock register
Alarm register 1
Not Implemented
System Status register
Not Implemented
Basic Configuration and Control register 0
Basic Configuration and Control register 1
Interrupt Delay register
AALx Control register
Not Implemented
Segmentation Control register
SEG VCC Table and Schedule Table Base Address register
SEG PM Table and Bucket Table Base Address register
Segmentation Transmit Queue Base register
Base Address of Routing Tag Table
Not Implemented
Schedule Priority Queue Control register 1
Schedule Priority Queue Control register 2
Schedule Size and Slot Minimum Drain Rate register
Scheduler Control register
Maximum ABR VCC_INDEX register
Schedule ABR Constant register
ABR Decision Table Lookup Base register
ABR Congestion Notification register
PCR Queue Interval 0 and 1 register
PCR Queue Interval 2 and 3 register
Not Implemented
Reassembly Control register 0
Reassembly Control register 1
Reassembly Free Buffer Queue Base register
Reassembly Free Buffer Queue Control register
Reassembly Table Base register
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
28236-DSH-001-B
CN8236