CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 282

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

11.0 PCI Bus Interface
11.3 PCI Configuration Space
11-4
11.3 PCI Configuration Space
In accordance with the PCI Bus Specification, Revision 2.1, the CN8236 PCI bus
interface implements a 128-byte configuration register space. These
configuration registers can be used by the host processor to initialize, control, and
monitor the SAR bus interface logic. The complete definitions of these registers
and the relevant fields within them is given in the PCI bus specification. (The
descriptions and definitions of these register fields as implemented in the
CN8236 are provided in
8 KB depending on the value of the INCFIFO_SZ bit in the CONFIG1 register.
11.4 PCI Bus Master Logic
The PCI bus master logic block is responsible for accepting read and write
commands from the DMA coprocessor (passed via the burst FIFO buffers), and in
turn acquiring mastership of the PCI bus and generating transactions to perform
the actual data transfers. The bus master logic contains the following:
read or a write transfer, using the defined PCI protocol sequence. In this case, the
bus master logic terminates the current burst, maintain its bus request, and
restarts the transfer at the point of termination. Disconnects and retries are not
regarded as errors.
The incoming DMA FIFO size is programmable and can be set to 2 KB or
• A command decoder that interprets commands issued from the DMA
• A burst controller that counts off read and write cycles in each burst on the
• Arbitration logic that acquires control of the PCI bus.
• Supported arbitration parking.
• A bus state machine that sequences and controls transfers.
It is possible for the addressed slave to request a disconnect or a retry during a
coprocessor.
PCI bus (and also latches and drives the address and command during the
address phase of each transfer).
Mindspeed Technologies
Chapter
ATM ServiceSAR Plus with xBR Traffic Management
14.0.)
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28236-DSH-001-B
CN8236