CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 278

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CN8236EBGB

Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet

Specifications of CN8236EBGB

Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V

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10.0 Local Processor Interface
10.9 CN8236 Reset
10-20
10.9 CN8236 Reset
The CN8236 must be reset by the host processor prior to system initialization for
proper operation. This can be done in one of two ways: by asserting the external
HRST* pin (which is normally connected to the system power-up reset circuitry),
or by setting the GLOBAL_RESET bit in the Configuration register 0
[CONFIG0;0x14]. The HRST* pin must be deasserted and GLOBAL_RESET
must be cleared before beginning the CN8236 initialization process.
pin to be driven active. The reset to the local processor stays active until the
LP_ENABLE bit in the CONFIG0 register is set to a logic high. When using the
GLOBAL_RESET bit, the processor must manually set or clear the appropriate
bits in the CONFIG0 register.
Asserting the HRST* input pin automatically causes the local processor reset
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
CN8236

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