CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 137

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
5.4.9 Hardware PDU Time-Out
28236-DSH-001-B
5.4.9.1 Reassembly
Time-Out Processing
5.4.9.3 Timer Reset
Time-Out Process
5.4.9.2 Halting
The CN8236 automatically detects active CPCS-PDU time-out for reassembly
channels. A PDU time-out occurs when a partially received PDU does not
complete within a set time period. When it detects this time-out condition, the
CN8236 provides a status queue indication to the host. This indication allows the
host to recover the buffers held by the partially completed PDU. The CN8236
supports up to eight reassembly time-out periods.
A background hardware process performs the reassembly time-out function. The
process is activated at a user-selected interval. The process is globally enabled by
setting the GTO_EN bit in the RSM_CTRL0 register. Once the RSM_TO register
is enabled, it controls the process activity. The process is activated every
RSM_TO_PER rising edges of SYSCLK on cell boundaries.
NOTE:
TO_VCC_INDEX. This is a 16-bit variable located at address 0x1350, in internal
SRAM. The host should initialize this register to 0 at system initialization.
in the VCC table entry. The host also assigns one of eight time-out periods to each
VCC by initializing the TO_INDEX field in the VCC table entry.
ACT_PDU, to see if time-out processing is enabled and necessary, respectively,
for the current connection. If either bit is 0, TO_VCC_INDEX is incremented by
1 and compared to RSM_TO_CNT in the RSM_TO register. If TO_VCC_INDEX
= RSM_TO_CNT, TO_VCC_INDEX is reset to 0, and the time-out search is
restarted at the beginning of the VCC table.
table entry. It then compares CUR_TOCNT to the time-out value selected,
TERM_TOCNTx, where x = TO_INDEX. TERM_TOCNT0 through
TERM_TOCNT7 are located at address 0x1340 through 0x134c in internal
SRAM. They must be initialized to appropriate values during system
initialization.
the current VCC. The CN8236 follows the procedure described in
Section
To halt time-out processing, the host “must” set the TO_LAST bit to 1 in the
RSM VCC table entry for the last VCC_INDEX that the host needs enabled for
time-out processing. When the CN8236 detects this bit set to 1, it halts time-out
processing.
the VCC is not checked for a time-out condition. The CN8236 simply increments
TO_VCC_INDEX and compares it to RSM_TO_CNT. If they are equal,
TO_VCC_INDEX is reset to 0, and the full time-out processing is re-enabled.
The CN8236 reassembly time-out process increments the CUR_TOCNT value. If
it reaches a threshold value, a time-out condition has occurred. In AAL5 and
AAL0, PTI termination modes, the reception of a non-EOM cell resets the
counter.
Each time the process is activated, it examines a single VCC, identified by
To enable hardware time-out on an individual VCC, the host must set TO_EN
The CN8236 checks the TO_EN bit and the active PDU indicator bit,
If both bits are set, the CN8236 increments CUR_TOCNT in the RSM VCC
If CUR_TOCNT = TERM_TOCNTx, a time-out condition has occurred on
When time-out processing is halted, the time-out process is still activated, but
GTO_EN set to 0 resets the internal time-out interrupt counter.
5.4.9.4.
Mindspeed Technologies
™
5.0 Reassembly Coprocessor
5.4 Buffer Management
5-27