CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 75

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 3-4. Write-only Control Queue
28236-DSH-001-B
READ_UD
3.3.1.3 Underflow
Conditions
WRITE++
Boundary
PCI Bus
submits a new entry, it must first ensure that the SAR has already processed the
entry location. The host compares WRITE to READ_UD. If (WRITE+1) modulo
size_of_queue equals READ_UD, the host halts writing to the queue. This results
in being able to use only N-1 queue entries. However, if this is not done, then a
full condition cannot be distinguished from an empty condition. The host must
wait until READ_UD is modified by the SAR before proceeding. This algorithm
ensures that the host does not overflow the control queue, without reading the
queue itself.
increments its write pointer (WRITE++). During this write, the host sets the valid
bit (VLD) in the entry to 1.
detected to a specific queue, the SAR attempts to process the queue entry at
READ. Before acting on the entry, the SAR checks for ownership of the entry,
indicated by the VLD bit. Once the CN8236 has processed the entry, it resets the
VLD bit to 0.
An underflow condition occurs when the SAR attempts to retrieve a queue entry
and the host has not yet supplied this entry. This condition happens only on the
free buffer queues. The SAR detects this condition by checking the queue entry
VLD bit. Once detected, the SAR enters an Underflow Detected state on this
queue only. Since this signifies that no data buffers are available for reassembly,
the SAR initiates EPD on all channels assigned to this queue.
describes SAR handling of free buffer queue underflow in detail.
The host also maintains a pointer into the queue, WRITE. When the host
Once it has verified its ownership of the entry, the host writes the entry and
The CN8236 snoops the writes to the control queue areas. Once a write is
READ_UD_PNTR=
VLD
bit
Update Host
Mindspeed Technologies
UPDATE=0
READ
0 0 0 0 0 0 0 0
Y
1
1 1 1 1 1 1 1 1
INTERVAL
UPDATE=
N
1
1
™
1 1 1 1 1 1 1 1 1
(Base Table)
UPDATE++
3.3 Write-only Control and Status
0 0 0 0
Chapter 5.0
3.0 Host Interface
READ++
Base
Register
8236_101
3-7