CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 341

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
0x114—Transmit Port Register (TX_FIFO_CTRL)
This register sets a counter compare value that is used for the head of line flushing mechanism of the transmit
FIFO. If head of line flushing is enabled in Configuration register 1, a counter is reset when the UTOPIA master
in multi-PHY mode puts out the address of a PHY device, and the counter is increased based on UTOPIA
tx_clk. Once the counter reaches the TX_CNTR value and no UTOPIA CLAV signal have been received from
the PHY device, the cell in the FIFO is discarded. TX_CNTR must not have a value of 0 if the head of line
flushing mechanism is enabled.
0x118—Transmit Port Control Register
This register disables UTOPIA ports if the TX_FIFO_FLUSH_EN bit in Configuration register 1 is set. If bit x
of the TX_PORT_DIS bitmap is set, cells belonging to PHY x are being discarded. No TX_STATUS bit are set.
28236-DSH-001-B
31–16
31–8
15–0
7–0
Bit
Bit
Field
Field
Size
Size
24
16
16
8
Reserved
TX_CNTR
Reserved
TX_PORT_DIS[7:0]
Name
Name
Mindspeed Technologies
Set to 0.
Counter Values to Tx FIFO flush mechanism.
Set to 0.
Disables PHY port x.
™
Description
Description
14.5 Reassembly Registers
14.0 CN8236 Registers
14-25