CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 272
CN8236EBGB
Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236EBGB.pdf
(443 pages)
Specifications of CN8236EBGB
Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
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10.0 Local Processor Interface
10.6 Standalone Operation
Table 10-2. Standalone Interface Pins
10-14
PROCMODE
PCS*
PBLAST*
PAS*
PWNR
PRDY*
PWAIT*
PDAEN*
PADDR[1:0]
PBSEL[1:0]
PBE[3:0]*
PFAIL*
NOTE(S):
(1)
(2)
Direction given with respect to the CN8236.
See the HOST_ISTAT0 register for details.
Signal
Dir
O
O
O
O
O
I
I
I
I
I
I
I
(1)
10.6 Standalone Operation
Standalone interface pins and descriptions are given in
shows the signal interface between the CN8236 and the RS825x ATM
receiver/transmitter device with no local processor. The PCS*, PAS*, and PWNR
pins are now outputs providing chip select, address strobe, and write/read control
to the RS825x. PDAEN* is now an input connected to the interrupt sources of the
RS825x. PBLAST* is a second chip select, which can be used to connect a future
second Mindspeed PHY device. The PRDY* output is active and indicates the
cycles in which the data transaction occurs. The PWAIT* input is active and can
be used to prolong the cycle (as shown in
other than the RS825x can be connected by using PWAIT* to extend the read or
write cycle, and by using external logic to translate the CN8236 control signals.
Processor interface mode select input. A logic 1 enables standalone operation without a
local processor.
Chip select output for PHY device number 1. Synchronous to SYSCLK.
Chip select output for PHY device number two. Synchronous to SYSCLK.
PHY address strobe. Synchronous to SYSCLK.
PHY write/read select. A logic 1 on this output indicates a write cycle, a logic 0 indicates a
read cycle. Synchronous to SYSCLK.
PHY interface ready signal. A logic low on this signal at rising edge of SYSCLK indicates
that the data cycle has been completed.
PHY wait input. Allows external logic to insert wait states to extend data cycles. Only
active when PRDY* is active.
PHY interrupt input, active low, level sensitive
Not used, pull to logic 0.
Not used, pull to logic 0.
Not used, pull to logic 0.
Not used, pull to logic 1.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
Description
™
Figure
(2)
.
10-9). Physical interface devices
Table
10-2.
28236-DSH-001-B
Figure 10-8
CN8236
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