CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 262

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

10.0 Local Processor Interface
10.2 Interface Pin Descriptions
Table 10-1. Processor Interface Pins (2 of 2)
10-4
PBE[3:0]*
PWAIT*
PBLAST*
PRDY*
PFAIL*
NOTE(S):
(1)
(2)
3. The processor system is responsible for controlling the direction of the bidirectional data bus transceiver. In the i960
Direction given with respect to the CN8236.
This output corresponds to the READY* or RDYRCV* input in the i960 architecture.
architecture, this can be controlled by the DT/R* signal.
Signal
Dir
O
I
I
I
I
(1)
Byte select inputs—Active low. Allows individual bytes of selected word to be written. Not
active on reads. Latched at rising edge of SYSCLK when PAS* and PCS* active. PBE[3]*
controls writes to LDATA[31:24]; PBE[2]* controls LDATA[23:16]; etc.
Processor wait input—Allows the processor to insert a variable number of wait states to
extend memory transaction. Must be active on rising edge of SYSCLK with PRDY* active
to insert wait cycle. Can be used to interface to half speed or slow processor bus or to
allow the use of slow transceivers. If insertion of wait states is not required, set this input
to a logic high. This signal can only be active, logic low, when PBLAST* is a logic high.
Processor burst last input—Indicates the last word of a cycle. Must be active on rising
edge of SYSCLK with PRDY* active to indicate last cycle. If burst accesses and wait cycles
generated by PWAIT* are not required, this signal should be set to a logic low.
Processor interface ready signal—A logic low on this signal at rising edge of SYSCLK
indicates that the present cycle has been completed. If a read cycle, the data is valid to
latch by the processor; if a write cycle, the data has been written and can be removed from
the bus. When PRDY* is active, wait states can be inserted with PWAIT*, or a single or
burst cycle can be terminated by PBLAST*
The local processor can indicate a failure of its internal self-test or initialization processes
by asserting the PFAIL* input to the CN8236.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
Description
(2)
™
.
28236-DSH-001-B
CN8236