CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 359

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 14-15. PCI Special Status Register
Table 14-16. EEPROM Register (1 of 2)
28236-DSH-001-B
NOTE(S):
(1)
28–23
22–16
15–12
7–0
Bit
31
30
29
11
10
9
8
Can be loaded from EEPROM.
Bit
31
Field
Size
1
1
1
6
7
4
1
1
1
1
8
Field Size
EN_SID_WR
MSTR_CTRL_SWAP
SLAVE_SWAP
Reserved
Memory Size Mask
Reserved
INTF_DIS
INT_FAIL
MERROR
MRD
Reserved
1
Name
(1)
BUSY
(1)
(1)
Name
Mindspeed Technologies
Enable SVID/SID Write. Default = 0.
Enable byte swapping on control words that the SAR writes. Default = low.
Enable byte swapping on control words of a slave write or read access.
Default = low.
Set to 0b000000.
A 7-bit mask which sets one of a range of values for the size of the PCI
address space. Default = 0000000.
Set to 0.
Master Interface Disabled. If the M_EN bit in the COMMAND field is a logic
low, any attempt by the CN8236 to perform a DMA transaction to the PCI
bus results in an error. INTF_DIS and MERROR bits set to a logic high.
This bit can be reset by writing a logic high to itself.
Master Interface Failed. Set to a logic high when an internal PCI/DMA
synchronization error has occurred. The MERROR bit is also set to a logic
high. This bit can be reset by writing a logic high to itself.
Memory Error. Indicates that the PCI bus master has encountered a fatal
error and therefore has halted operation. Set when either RTA, RMA, DPR,
INTF_DIS, or INT_FAIL errors occur. This bit can be reset by writing a logic
high to itself.
Error on Master Read/Write. If a logic high, indicates that the errored
transaction was a read, and the address of the read is located in the
MASTER_READ_ADDR field. If a logic low, indicates the errored
transaction was a write and the corresponding address is located in the
MASTER_WRITE_ADDR field.
Set to 0x00.
0000000 = 8 M
Indicates that an EEPROM operation is currently in progress. This
bit must be read as a 0 before initiating an EEPROM transfer.
™
Description
Description
14.7 PCI Bus Interface Registers
14.0 CN8236 Registers
14-43