CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 375

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
15.4.1 General Control Registers
Table 15-9. Table of Values for General Control Register Initialization (1 of 2)
28236-DSH-001-B
CONFIG0
(Configuration Register 0)
INT_DELAY
(Interrupt Delay Register)
Register
15.4 General Initialization
Before the SAR is enabled, the host must allocate and initialize all of the general
SAR control registers.
LP_ENABLE
GLOBAL_RESET
PCI_MSTR_RESET
PCI_ERR_RESET
INT_LBANK
PCI_READ_MULTI
PCI_ARB
STATMODE
FR_RMODE
FR_LOOP
UTOPIA_MODE
LP_BWAIT
MEMCTRL
BANKSIZE
DIVIDER
Reserved
TIMER_LOC
EN_TIMER
EN_STAT_CNT
STAT_CNT[7:0]
Mindspeed Technologies
Field
Table 15-9
Initialized
Value
0 – 1
0 – 1
0x35
0x0
0x3
0x0
0x0
1
0
0
0
0
1
1
0
0
0
0
0
1
lists the initialized values for each field.
™
15.0 SAR Initialization—Example Tables
Local processor not used.
This must be toggled to a logic high and
back to a logic low after completion of all
initialization, but before RSM and SEG
coprocessors are enabled.
Use GLOBAL_RESET to reset SAR.
Must be initialized to 0.
Should be set to 0 during initialization, but
set to one after system reset.
PCI Read Multiple Command used.
Round-robin arbitration of internal
read/write PCI master.
Selects BOM sync hardware mode.
Early RSM header processing enabled.
Internal ATM physical interface disabled.
Cell handshake mode selected.
Selects 0 wait states between consecutive
data cycles during local processor.
Selects 0 wait states SAR-shared memory.
512 kB banks selected.
Divide by 128 selected for CLOCK prescaler.
Must be initialized to 0.
Interrupt hold-off timer used with HINT*.
Disable status queue interrupt timer delay.
Enable status queue interrupt counter delay.
Interrupt delay counter set to 53.
Notes
15.4 General Initialization
15-15