CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 185

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 6-10. CDV Caused by Schedule Table Size at Certain CBR Rates
28236-DSH-001-B
from slot 99 to slot 00.)
(Scheduler wraps
00 01
02 03 04 05 06
9
CBR rates whose schedule slot spacings do not evenly divide the table slot size.
An example of this is illustrated in
100-slot Schedule table is shown. The system designer has reserved bandwidth
for CBR channel C at a rate of 32.25 K cells/second, or every ninth cell slot.
When the Scheduler wraps from the end of the table to the beginning of the table,
the number of schedule slots between the last C channel slot at the end of the table
and the first C channel slot at the beginning of the table is 10 slots, not 9.
Section
The FIFO buffer introduces worst case CDV when one CBR cell is transmitted
through an empty FIFO buffer, and the next CBR cell from that channel is
segmented to a full FIFO buffer.
register. By reducing the TX_FIFO_LEN, the system designer reduces CDV.
However, the TX_FIFO also absorbs PCI bus latency. To prevent PCI latency
from impacting line utilization, set the TX_FIFO length according to the
following formula:
Another possible source of Schedule-table-dependent CDV occurs for certain
The worst-case CDV is determined by the following formula:
The first term in the formula above is introduced by CBR Rate Matching (see
The second term in the formula above is introduced by the TX_FIFO itself.
The system designer programs the TX_FIFO_LEN in the SEG_CTRL
CDV
07 08 09 10
6.2.2.4).
Mindspeed Technologies
max
TX_FIFO_LEN > 1
C
=
85
Schedule Table
9
1 (CBR rate in cells sec)
86 87 88 89
11 12
+
(worst case PCI latency) (line rate in cells sec)
C
9
13 14 15 16
Figure
90 91
+
™
6.2 xBR Cell Scheduler Functional Description
TX_FIFO_LEN (line rate in cells sec)
6-10, where the beginning and end of a
92 93 94 95
17 18 19
C
9
6.0 Traffic Management
96 97 98
20
9
C
99
8236_042
6-17