CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 81
CN8236EBGB
Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236EBGB.pdf
(443 pages)
Specifications of CN8236EBGB
Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
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CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 4-1. Segmentation VCC Table
28236-DSH-001-B
(SEG_VBASE(SEG_VCCB)<<5)
Identification
4.2.1.2 VCC
Base Register
VCC_INDEX = 0xFFFD
VCC_INDEX = 0x1000
classes. This includes a default ATM header, which the host can modify during
the segmentation process. See
segmentation VCC table entry.
The host allocates a region of SAR-shared memory for the segmentation VCC
table at system initialization, based on the maximum number of connections and
the maximum number of ABR connections. The host informs the SAR of the
location of the table through the internal base register, SEG_VBASE
(SEG_VCCB).
entries in the table. The host describes the SEG VCC by initializing the SEG VCC
table entry including the SCH_STATE portions of the assigned VCC. The
VCC_INDEX, defined as the offset into the table in 10-word increments,
uniquely identifies a segmentation channel. In all communication between the
SAR and the host, a VCC_INDEX field specifies a VCC.
(non-ABR VCC)
VCC_INDEX = 0x3
The VCC table entry contains generic information common to all traffic
Once a table has been established, the host assigns segmentation VCCs to
(ABR VCC)
(CBR VCC)
Mindspeed Technologies
VCC Table Entry
VCC Table Entry
VCC Table Entry
SCH_STATE
SCH_STATE
SCH_STATE
VCC Table
Section
VCC_INDEX = 0x0
}
}
}
}
}
10 Words = 1 Descriptor
7 Words
7 Words
13 Words
3 Words
4.3.1, for full details of the structure of a
™
4.2 Segmentation Functional Description
}
}
2 Descriptors
1 Descriptor
4.0 Segmentation Coprocessor
8236_095
4-3
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