CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 345
CN8236EBGB
Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236EBGB.pdf
(443 pages)
Specifications of CN8236EBGB
Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
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CN8236
ATM ServiceSAR Plus with xBR Traffic Management
14.6.1 Host Interrupt Status Registers
These two registers contain all interruptible status bits for the host processor. The corresponding interrupt
enables are located in the HOST_IMASKx registers. Status types are defined as follows:
28236-DSH-001-B
DE
L
E
Mindspeed Technologies
NOTE:
Level-sensitive status—A logic 1 on the status bit causes an interrupt
when enabled by the corresponding IMASK bit. Reading the status
does not clear the status or interrupt. The source of the condition
causing the status must be cleared before the status or interrupt is
cleared.
Event driven status—A 0 > 1 transition on the status bit causes an
interrupt when enabled. Reading the status register clears the status bit
and the interrupt.
Dual Event status—A 0 > 1 and 1 > 0 transition on the status bit can
be enabled to cause an interrupt. Reading the status register clears the
status bit and the interrupt.
Only host reads reset the status bits in the HOST_ISTAT0
register.
™
14.6 Counters and Status Registers
14.0 CN8236 Registers
14-29
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