CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 184

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

6.0 Traffic Management
6.2 xBR Cell Scheduler Functional Description
Figure 6-8. Introduction of CDV at the ATM/PHY Layer Interface
Figure 6-9. Schedule Table with Slot Conflicts at Different CBR Rates
6-16
6.2.3.3 CBR Cell Delay
A
00 01
Variation (CDV)
Cell Scheduler
B
02 03 04 05 06
5
4
A
CBR connections are sensitive to CDV. (See ATM Forum UNI 3.1 or TM 4.1 for a
complete definition of CDV.) The CN8236’s Traffic Manager minimizes CDV by
basing all traffic management on the Scheduler clock frequency and providing the
user the ability to explicitly decide the transmit time for CBR traffic. However, no
system is without some CDV. In the case of terminals using the CN8236, the
dominant factor in CDV is the variation introduced between the segmentation
coprocessor and the PHY layer device at the Transmit FIFO buffer (TX_FIFO).
Line overhead created by the framer in the PHY layer device causes this variation.
Figure 6-8
contracts for different CBR rates on more than one CBR channel, causing
schedule slot conflicts in the Schedule table.
a linear representation of a Schedule table with 100 schedule slots. CBR channel
A has reserved bandwidth for a rate of 70 K cells/second, or every fifth cell slot.
CBR channel B has reserved bandwidth for a rate of 88.7 K cells/second, or every
fourth cell slot. In this case there is a schedule slot reservation conflict between
channels A and B every 20th cell slot, and one of the channel’s slots has to be
reserved one slot later.
B
A possible source of Schedule table-dependent CDV is created when the host
07 08 09 10
5
4
Mindspeed Technologies
illustrates this interface.
Segmentation
Coprocessor
Schedule Table
A
B
11 12
4
5
13 14 15 16
ATM ServiceSAR Plus with xBR Traffic Management
B
A
PHY Interface
4
™
Cells are added at CBR rate
17 18 19
Figure 6-9
5
(Line rate — Line overhead)
B
(1-9 Cells)
TX_FIFO
Cells are removed at
illustrates an example of
4
A
20 21
28236-DSH-001-B
B
22
23
CN8236
8236_040
8236_041