ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 10

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ORCA ORT8850 Data Sheet
ter and slave elements are also available for the user-logic and embedded backplane transceiver portion of the
ORT8850.
The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset func-
tions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is
integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the Micro-
Processor Interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from
routing, or from the port clock (for JTAG configuration modes).
Phase-Locked Loops
Four user PLLs are provided for ORCA Series 4 FPSCs. Programmable PLLs can be used to manipulate the fre-
quency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks
from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/64x to 64x the input clock frequency. Each program-
mable PLL provides two outputs that have different multiplication factors but can have the same phase relation-
ships. Duty cycles and phase delays can be adjusted in 12.5% increments of the clock period. An automatic input
buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have pro-
grammable (12.5% steps) phase differences.
Embedded Block RAM
New 512 x 18 quad-port RAM blocks are embedded in the FPGA core to significantly increase the amount of mem-
ory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two
byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available,
as well as direct connection to the high-speed system bus.
Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable
multiply functions. The user can configure FIFO blocks with flexible depths of 512k, 256k, and 1k including asyn-
chronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple
of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-
bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit
CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can
also be preloaded at device configuration time.
Configuration
The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configura-
tion circuitry loads the configuration data at power-up or under system control. The configuration data can reside
externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for
configuring FPGAs.
The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial,
master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its MicroProcessor Interface
and embedded system bus to perform both programming and readback. Daisy chaining of multiple devices and
partial reconfiguration are also permitted.
Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as
well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE
1149.2 ) port is also available meeting In-System Programming (ISP) standards ( IEEE 1532 Draft).
Additional Information
Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPSC and FPGA
devices, or visit our website at www.latticesemi.com.
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