ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 31

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Serial TOH Insertion Mode
In the transmit direction the SPE bytes are always transferred unaltered from the input parallel bus to the serial
LVDS output. On the other hand, TOH bytes are received from the serial input port and are inserted in the STS-12
frame before being sent to the LVDS output in the Serial TOH Insertion mode. The FPGA logic must provide fram-
ing information to the Core using the TX_TOH_CK_EN Input signal. TOH data is input on a row by row basis, with a
one clock cycle frame pulse delineating the start of a row, as shown in Figure 14. As shown in the figure, while the
SPE bytes are being transmitted for one row, the FPGA logic must simultaneously supply the Core with the TOH
data for the next row. Detailed timing for the TOH serial input is shown later in Figure 31.
Figure 14. TOH Serial Port Input Framing Signals (FPGA to Core)
Incoming serial TOH data is synchronized initially to the free running clock, TOH_CLK. TOH_CLK can operate from
a minimum frequency of 25 Mhz. to a maximum frequency of 106 MHz. TOH bytes are transferred in the order
shown in Figure 15. Bytes are transferred over the serial links with the MSB first. Data should be transferred over
the serial link on a row-by-row basis. With three TOH bytes/per row for each STS-1 stream and a total of 12 STS-1
streams per STS-12 frame, a total of 288 TOH bits must be transferred for each row. The 288 TOH bits per row can
be sent back-to-back. In this case, TX_TO_CLK_EN will be high continuously for 288 TOH_CLK cycles.
It is the responsibility of the user to synchronize transfer of the TOH bytes to a pre-determined window of time rela-
tive to the STS-12 frame position on the parallel input bus, i.e., the 36 TOH bytes to be inserted in row number n
must be transferred to the Core during the time the SPE bytes of row n-1 are being transferred to the Core over the
parallel input bus. Within each SPE row, a guard band of four TOH_CLK cycles must be provided on each side of
the TOH transfer window. No data may be transferred in these guard bands.
FPGA_SYSCLK
SYS_FP
DINxx[7:0]
TOH_CLK
TX_TOH_CK_EN
TOH_INxx
Row 1
36 bytes TOH
MSbit(7)
of B1 byte STS1 #1
31
bit 6
of B1 byte STS1 #1
ORCA ORT8850 Data Sheet