ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 49

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 15. FPGA/Embedded Core Interface Signals (Continued)
Clock and Data Timing at the FPGA/Embedded Core Interface - SONET Block
(Note: This section assumes a basic understanding of the Lattice Semiconductor ispLEVER design tool set)
This section provides examples of the clock and data timing relationships at the FPGA/Embedded Core interface
for both the parallel SONET data and the serial TOH data. The initiation of a change of data is referred to as the
"launch" time and the actual time of capture of the data is referred to as the "capture" time. Two relationships are
discussed, the relationship between data and clock at the interface itself and the relative timing constraints on the
signals in the FPGA logic between the interface and the launch/capture latch in the FPGA portion of the FPSC.
The ispLEVER place and route tool will automatically attempt to meet the timing constraints by placing a frequency
constraint on the corresponding clock and will report a non-routed condition if it is unable to do so. Trace reports
should also be generated using ispLEVER to evaluate both the setup and the hold margins.
The typical timing numbers used in the discussions are for illustration purposes and can vary due to both process
and environmental variations and to differences in the routing through the FPGA logic, especially for the data path.
Exact timing numbers should always be obtained from ispLEVER.
In all of the discussions in this section, the maximum reference clock frequency of 106 MHz is assumed. The pri-
mary clock path delay was assumed to be 3 ns - this delay is well controlled in the FPGA logic. A secondary clock
path delay can vary from 1 to 3.5 ns - a delay of 2.5 ns was used in the payload data discussions and 2 ns for the
TOH discussions.
The five cases considered in the discussion are shown in Table 16. The clock routing and timing configurations
shown in this section are recommended for the general user since they give the best timing margins. In the discus-
sion, if both the core and FPGA launch and latch data on the same edge, it is referred to as a "full cycle" mode. If
they launch and latch on different edges, it is referred to as a "half cycle" mode.
TOH_xx_EN
Protection Switching Signals (Note: See also Table 17 and Table 18)
PROT_SWITCH_AA
PROT_SWITCH_AC
PROT_SWITCH_BA
PROT_SWITCH_BC
LVDS_PROT_AA
LVSD_PROT_AB
LVDS_PROT_AC
LVDS_PROT_AD
LVDS_PROT_BA
LVDS_PROT_BB
LVDS_PROT_BC
LVDS_PROT_BD
FPGA/Embedded Core
Interface Signal Name
xx=[AA,…,BD]
ORT8850 FPGA/Embedded Core Interface Signals - SONET Blocks
Input (I) to or Output (O)
from Core
O
I
I
I
I
I
I
I
I
I
I
I
I
Indicates state of register settings for TOHxx_EN
Parallel protection switch select, Channels AA and AB
Parallel protection switch select, Channels AC and AD
Parallel protection switch select, Channels BA and BB
Parallel protection switch select, Channels BC and BD
LVDS protection switch select, Channel AA
LVDS protection switch select, Channel AB
LVDS protection switch select, Channel AC
LVDS protection switch select, Channel AD
LVDS protection switch select, Channel BA
LVDS protection switch select, Channel BB
LVDS protection switch select, Channel BC
LVDS protection switch select, Channel BD
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Signal Description
ORCA ORT8850 Data Sheet