ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 78

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Table 32. FPGA Common-Function Pin Descriptions (Continued)
Lattice Semiconductor
Special-Purpose Pins
M[3:0]
PLL_CK[0:7][TC]
P[TBLR]CLK[1:0][T
C]
TDI, TCK, TMS
RDY/BUSY/RCLK
HDC
LDC
INIT
CS0, CS1
RD/MPI_STRB
WR/MPI_RW
PPC_A[14:31]
MPI_BURST
1. The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activa-
tion of all user I/Os) is controlled by a second set of options.
Symbol
I/O
I/O After configuration, these pins are user-programmable I/O.*
I/O These pins are user-programmable I/O pins if not used by PLLs after configuration.
I/O After configuration these pins are user-programmable I/O, if not used for clock inputs.
I/O After configuration, these pins are user-programmable I/O in boundary scan is not used.*
I/O After configuration this pin is a user-programmable I/O pin.*
I/O After configuration, this pin is a user-programmable I/O pin.*
I/O After configuration, this pin is a user-programmable I/O pin.*
I/O
I/O After configuration, if MPI is not used, these pins are user-programmable I/O pins.*
I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.*
O
O
O
I
I
I
I
I
I
I
I
I
During power-up and initialization, M0—M3 are used to select the configuration mode with their val-
ues latched on the rising edge of INIT . During configuration, a pull-up is enabled.
Semi-dedicated PLL clock pins. During configuration they are 3-stated with a pull up.
Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing.
If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is com-
plete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during configu-
ration. Each pin has a pull-up enabled during configuration.
During configuration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
During the master parallel configuration mode, RCLK is a read output signal to an external memory.
This output is not normally used.
High during configuration is output high until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
Low during configuration is output low until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT
is held low during power stabilization and internal clearing of memory. As an active-low input, INIT
holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin.*
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configu-
ration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-
up is enabled.
RD is used in the asynchronous peripheral configuration mode. A low on RD changes D[7:3] into a
status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides.
This pin is also used as the
and a low indicates busy.
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write trans-
fer to the FPGA.
During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus mas-
ter utilizing the least-significant bits of the PowerPC 32-bit address.
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indi-
cates that the current transfer is not a burst.
MPI
data transfer strobe. As a status indication, a high indicates ready,
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Description
ORCA ORT8850 Data Sheet