ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 34

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Scrambling
To ensure a 1's density for the SERDES the data stream is scrambled using a frame-synchronous scrambler with a
sequence length of 127. The scrambling function can be disabled by setting a control register bit (0x3000C). The
generating polynomial for the scrambler is 1 + x
data format. The scrambler is reset to 1111111 on the first byte of the SPE (byte following the Z0 byte in the twelfth
STS-1). The scrambler runs continuously from that byte on throughout the remainder of the frame. The A1, A2, J0,
and Z0 bytes are not scrambled.
After scrambling, the serial data is broadcast to both the work and protect LVDS buffers.
Receive Path Logic
Each of the two SONET logic blocks has four receiving channels which can be treated as one STS-48 stream or as
four independent STS-12 or STS-3 channels.The received data streams are processed and passed to the FPGA
logic.
When doing multichannel alignment of two or more data streams, the receiver can handle the data streams with
frame offsets of up to 18 bytes due to timing skews between cards and along backplane traces or other transmis-
sion medium. For multichannel alignment capability to operate properly, it should be noted that while the skew
between channels can be very large, they must operate at the exact same frequency (0 ppm frequency deviation),
thus requiring that the transmitters sourcing the data being received be driven by the same clock source.
Each STM block receives the serial streams of STS-12 data (maximum of four streams per quad) from the LVDS
inputs. There is no received clock input. There are two sets of receive LVDS pins, RXDxx_W_[P:N] and
RXDxx_P_[P:N]. If the LVDS protection switching is used, the RXDxx_W_[P:N] LVDS inputs are used to accept the
main data while the RXDxx_P_[P:N] LVDS inputs are used to accept the protect data.
Once the serial data is received from the LVDS inputs it goes through the following processing steps:
• The clock for the received data is recovered from the received serial data stream and a serial to parallel conver-
• The frame format of the incoming data is reconstructed (optional). The data is descrambled using the standard
• A B1 parity error check is performed on the data from the previously transmitted frame
• The channel alignment FIFO perform channel alignments on groups of incoming data streams (optional) and/or
• The SONET pointer interpreter and pointer mover detect the location of the SPE and C1J1 bytes and additionally
• The received parallel data, parity, recovered clock, SPE and C1J1 indicators and TOH parallel data is sent to the
These processing steps are described in more detail in the following sections. A block diagram of the receive path
logic is shown in Figure 16. All processing except the CDR functions (clock recovery and serial to parallel conver-
sion) is optional. If all processing except the SERDES is deselected, the device is said to be operating in the
"bypass" mode.
sion is performed on the data
STS-12 polynomial (optional)
simply perform the domain transfer from the recovered clock to the local reference clock.
inserts 0xFFs instead of received data into the data path, if an line Alarm Indication Signal (AIS-L) is detected.
The offset pointers are adjusted to point to the location of the J1 byte.
FPGA logic.
6
+ x
7
. This polynomial conforms to the standard SONET STS-12
34
ORCA ORT8850 Data Sheet