ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 16

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
this feature the alignment FIFO cannot be used with this clock architecture. The recovered clock is used for all
receive timing in the embedded core and supplied to the FPGA logic which must provide the clock domain transfer
functionality.
Figure 6. Independent Clock Architecture
SONET Bypass Mode
It is possible to utilize only the serializer and deserializer (SERDES) blocks in the ORT8850 and to bypass all of the
SONET framing and scrambling/descrambling. In this mode the parallel data from the FPGA is serialized and sent
out the LVDS pins. The serial data in the receive direction will be run through the SERDES and then received as
parallel data with a recovered clock into the FPGA.
In the SONET Bypass mode there exists half and quarter rate selection options. Half rate allows the SERDES to
operate at 4x the reference clock. When using half rate mode only the bits 7:4 of the parallel FPGA bus are utilized.
Quarter rate allows the SERDES to operate at 2x the reference clock. When using quarter rate mode only bits 7:6
of the parallel FPGA bus are utilized. Half rate and quarter rate are selectable per channel and can be mixed per
channel so that some channels can run in full rate mode while others operate in half rate mode and still others
operate in quarter rate mode.
As shown in Table 3, 63.00 MHz is the slowest reference clock and 106.25 MHz is the fastest reference clock fre-
quency supported. For all three modes, all bandwidths within the reference clock limits are supported. Note that
there are gaps between the bandwidths supported in the three modes.
Table 3. SONET Bypass Mode Bandwidth Options
In the SONET Bypass mode a 1's density function similar to SONET scrambling must be implemented in the FPGA
logic to assure reliable clock recovery at the receiver.
Cards
Reference Clock
Port
Osc.
Osc.
Osc.
106.25
77.76
63
System Diagram
504.00 Mbits/s
850.00 Mbits/s
Fabric
Cards
622.08Mbits/s
Full Mode
Osc.
Osc.
16
* Examples of
Typical Board
Components
Details
Board
Bits [7:4] Used
252.00 Mbits/s
425.00 Mbits/s
311.04Mbits/s
Half Mode
77.76 Mhz
Oscillator
(SERDES at
Buffer
LVDS
622 Mbps)
ORT8850
SYS_CLK_N
SN65LVDS31D*
HC54R8*
Winfield
Conner
Bits [7:6] Used
Quarter Mode
126.00 Mbits/s
212.50 Mbits/s
155.52Mbits/s
TI
ORCA ORT8850 Data Sheet
SYS_CLK_P
or
Differential
77.76 Mhz
Oscillator
Output