ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 23

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
reset and all the local bus interface signals forced high, but the following active-high signals, PROT_SWITCH_AA,
PROT_SWITCH_AC, PROT_SWITCH_BA, PROT_SWITCH_BC, TX_TOH_CK_EN, SYS_FP, LINE_FP, will be
forced low. The CORE_READY signal sent from the embedded core to FPGA is held low, indicating that the core is
not ready to interact with FPGA logic. At the end of the FPGA configuration sequence, the CORE_READY signal
will be held low for six SYS_CLK cycles after DONE, TRI_IO and RST_N (core global reset) are high. Then it will go
active-high, indicating the embedded core is ready to function and interact with FPGA programmable circuit. During
FPGA reconfiguration when DONE and TRI_IO are low, the CORE_READY signal sent from the core to FPGA will
be held low again to indicate the embedded core is not ready to interact with FPGA logic. During FPGA partial con-
figuration, CORE_READY stays active. The same FPGA configuration sequence described previously will repeat
again.
The initialization of the embedded core consists of two steps: register configuration and synchronization of the
alignment FIFO. The steps to configure the ORT8850 device for normal operation are listed in Table 4 and Table 5.
Generic Backplane Transceiver Application
Independent Channels, Transparent TOH: Table 4 lists the register values to setup the ORT8850 as eight inde-
pendent SONET channels (no alignment) using transparent TOH. The order is specific. The values are given from
the PowerPC point of view. If using the MPI to write data to the ORT8850, the value given in the table is the value
that should be used. If using the UMI of the system bus, the data value would need to be byte flipped.
Table 4. Independent Channels, Transparent TOH
0x30004
0x30005
0x30020
0x30021
0x30022
0x30038
0x30030
0x3003A
0x30050
0x30051
0x30052
0x30068
0x30069
0x3006A
0x30080
0x30081
0x30082
0x30098
0x30099
0x3009A
0x300B0
0x300B1
0x300B2
0x300C8
0x300C9
0x300CA
Register
Address
0x05
0x80
0x07
0xFF
0xFF
0x07
0xFF
0xFF
0x07
0xFF
0xFF
0x07
0xFF
0xFF
0x07
0xFF
0xFF
0x07
0xFF
0xFF
0x07
0xFF
0xFF
0x07
0xFF
0xFF
Value
Lock register. This value must be written to allow writing to any other ORT8850 core register
Lock register. This value must be written to allow writing to any other ORT8850 core register
Turn on Channel AA in functional mode
Channel AA - Transparent TOH from parallel data
Channel AA - Transparent TOH from parallel data
Turn on Channel AB in functional mode
Channel AB - Transparent TOH from parallel data
Channel AB - Transparent TOH from parallel data
Turn on Channel AC function mode
Channel AC - Transparent TOH from parallel data
Channel AB - Transparent TOH from parallel data
Turn on Channel AD in functional mode
Channel AD - Transparent TOH from parallel data
Channel AD - Transparent TOH from parallel data
Turn on Channel BA functional mode
Channel BA- Transparent TOH from parallel data
Channel AD - Transparent TOH from parallel data
Turn on Channel BB in functional mode
Channel BB- Transparent TOH from parallel data
Channel BB- Transparent TOH from parallel data
Turn on Channel BC in functional mode
Channel BC- Transparent TOH from parallel data
Channel BC - Transparent TOH from parallel data
Turn on Channel BD in functional mode
Channel BD - Transparent TOH from parallel data
Channel BD - Transparent TOH from parallel data
23
Description
ORCA ORT8850 Data Sheet