ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 80

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
This section describes device I/O signals to/from the embedded core.
Table 33. FPSC Embedded Core Function Pin Description (xx = AA, ..., BD)
HSI LVDS Receive Pins
HSI LVDS Transmit Pins
HSI Test Signals
LVDS Interface Special Pins
MISC System Signals
LVCTAP_W[4:0]
LVCTAP_P[4:0]
SCAN_TSTMD
TSTMUX[9:0]S
RXD
RXD
TXD
TSTSUFTLD
SYS_CLK_P
SYS_CLK_N
LVCTAP_SK
TXD
RXD
RXD
V
TXD
TXD
E_TOGGLE
V
DAUTREC
SCAN_EN
TESTRST
RESETTX
MRESET
EXDNUP
SSA
TSTCLK
DDA
RESLO
Symbol
RST_N
ELSEL
REF10
REF14
RESHI
XX
XX
XX
XX
XX
XX
XX
XX
_STM*
_STM
_W_N
_W_N
_W_P
_W_P
_P_P
_P_N
_P_P
_P_N
I/O
—
—
—
—
—
—
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Positive LVDS work link—Channel
Negative LVDS work link—Channel
Positive LVDS protect link—Channel
Negative LVDS protect link—Channel
Disable auto recovery for the PLL. Internal pull-down.
Analog V
Analog V
Positive LVDS work link—channel
Negative LVDS work link—channel
Positive LVDS protect link—channel
Negative LVDS protect link—channel
Test clock for emulation of 622 MHz clock during PLL bypass. Internal pull-
down.
Test mode reset. Internal pull-down.
Resets receiver clock division counter. Internal pull-up.
Resets transmitter clock division counter. Internal pull-up.
Test mode output port.
Test mode enable. Must be tie-low for normal operation.
Scan test enable. Internal pull-up.
Internal pull-down.
Internal pull-down.
Internal pull-down.
Internal pull-down.
LVDS work input center tap (use 0.01 µF to GND).
LVDS protect input center tap (use 0.01 µF to GND).
LVDS reference voltage: 1.0 V ± 3%.
LVDS reference voltage: 1.4 V ± 3%.
LVDS resistor high pin ( 100 Ω in series with reslo).
LVDS resistor low pin ( 100 Ω in series with reshi).
Reset the core only. The FPGA logic is not reset by rst_n.
Internal pull down allows chip to stay in reset state when external driver loses
power.
Positive LVDS system clock, 50% duty cycle, also the reference clock of PLL.
Negative LVDS system clock, 50% duty cycle, also the reference clock of
PLL.
LVDS center-tap for SYS_CLK (use 0.01 µf to GND).
DD
SS
for the HSI block.
1.5 V power supply for the HSI block.
80
Description
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ORCA ORT8850 Data Sheet