ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 51

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
tions. (The clock edge on which data is latched in the core is hard wired to be the falling edge.) Since the falling
edge of the clock (FPGA_CLK) at the FPGA latch occurs after the next data byte is launched, the delay from the
interface to the FPGA latch must be large enough that an acceptable hold time margin is obtained. However the
maximum propagation delay is fairly large, so a half cycle approach might lead to setup time problems.
Figure 27. Full Cycle, Alignment FIFO Bypass Mode Output Configuration and Timing (-1 Speed Grade)
CDR_CLK_xx
RETIME_CLK
DOUTxx[7:0]
a. Configuration
b. Timing (ns)
FPGA_CLK
FPGA_CLK
FPGA
Logic
tprop_min = 0.8
-
0.0
Secondary Clock
0.8
D
3.0 ns
2.5
Hold
4.7
5.5
Δt
Note: xx = [AA, AB, ..., BD]
7.2
tprop_max = 4.7
Launch
CDR_CLK_xx
DOUTxx[7:0]
9.4
10.2
51
11.9
Data Valid
14.1
Δt
0.5 ns
14.9
16.6
Q
Capture
18.8
ORCA ORT8850 Data Sheet
-
19.6
RETIME_CLK
Embedded
1.3 ns
Core
HSI_CLK