ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 4

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
FPGA Features
• High-performance platform design:
• Traditional I/O selections:
• New programmable high-speed I/O:
• New capability to (de)multiplex I/O signals:
• Enhanced twin-quad Programmable Function Unit (PFU):
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
• SLIC provides eight 3-State Buffers, up to 10-bit decoder, and PAL
• Improved built-in clock management with dual-output Programmable Phase-Locked Loops (PPLLs) provide opti-
previous architectures.
faster routing times with predictable and efficient performance.
grammable logic cell.
mum clock modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Mul-
tiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible.
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 600K FPGA system gates (ORT8850H).
– Meets multiple I/O interface standards.
– 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
– LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input flip-flop/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path.
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, LVPECL.
– LVDS include optional on-chip termination resistor per I/O and on-chip reference generation.
– New Double-Data Rate (DDR) on both input and output at rates up to 350 MHz (700 Mbits/s effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-
– New register control in each PFU has two independent programmable clocks, clock enables, local
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX,
– 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-
sink/3 mA source.
dently, plus one extra for arithmetic operations.
SET/RESET, and data selects.
and ripple mode arithmetic functions in the same PFU.
only eight PFUs) using the SLIC decoders as bank drivers.
internal routing, which reduces routing congestion and improves speed.
tions, with the option to register the PFU carry-out.
4
®
-like AND-OR-INVERT (AOI) in each pro-
ORCA ORT8850 Data Sheet