ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 79

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Table 32. FPGA Common-Function Pin Descriptions (Continued)
Lattice Semiconductor
MPI_BDIP
MPI_TSZ[0:1]
A[21:0]
MPI_ACK
MPI_CLK
MPI_TEA
MPI_RTRY
D[0:31]
DP[0:3]
DIN
DOUT
TESTCFG
LVDS_R
1. The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activa-
tion of all user I/Os) is controlled by a second set of options.
Symbol
I/O
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
I/O
I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.*
I/O
I/O After configuration, this pin is a user-programmable I/O pin.*
I/O After configuration, DOUT is a user-programmable I/O pin.*
I/O After configuration, TESTCFG is a user programmable I/O pin.*
— Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS inputs.
O During master parallel mode A[21:0] address the configuration EPROMs up to 4M bytes.
O
O
O This pin requests the MPC860 to relinquish the bus and retry the cycle.
O D[7:3] output internal status for asynchronous peripheral mode when RD is low.
O
I
I
I
I
I
I
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the
second beat in front of the current one is requested by the master. Negated before the burst transfer
ends to abort the burst data phase.
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for
the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
In
data on a read cycle.
This is the PowerPC synchronous, positive-edge bus clock used for the
source of the clock for the embedded system bus. If MPI is used this will be the AMBA bus clock.
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the inter-
nal system bus for the current transaction.
Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write trans-
action and driven by MPI in a read transaction.
D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration
modes when WR is low and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input.
Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2]
for D[16:23], and DP[3] for D[24:31].
After configuration, if MPI is not used, the pins are user-programmable I/O pin.*
During slave serial or master serial configuration modes, DIN accepts serial configuration data syn-
chronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration,
a pull-up is enabled.
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave
devices. Data out on DOUT changes on the rising edge of CCLK.
During configuration this pin should be held high, to allow configuration to occur. A pull up is
enabled during configuration.
MPI
mode this is driven low indicating the MPI received the data on the write cycle or returned
79
Description
ORCA ORT8850 Data Sheet
MPI
interface. It can be a