ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 33

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 10. Transmitter TOH on LVDS Output (TOH Insert Mode)
Repeater
This block is essentially the inverse of the sampler block discussed in the receive path description section. It
receives byte-wide STS-12 rate data from the TOH insert block. In order to support the STS-3 mode of operation,
the HSI (622 Mbits/s) can be connected to a slower speed device (e.g., 155 Mbits/s). The purpose of this block is to
rearrange the data being fed to the HSI so that each bit is transmitted four times, thus simulating 155 Mbits/s serial
data. In STS-3 mode, the incoming STS-12 stream is composed of four identical STS-3s so only every fourth byte
is used. The bit expansion process takes a single byte and stretches it to take up 4 bytes each consisting of 4 cop-
ies of the 8 bits from the original byte.
A1/A2 Processing
The A1 and A2 bytes provide a special framing pattern that indicates where a STS-1 begins in a bit stream. All 12
A1 bytes of each STS-12 are set to 0xF6, and all 12 A2 bytes are set to 0x28 automatically by the SONET framer.
The latency from the transmit of the first bit of the A1 byte at the device output pins from the system frame pulse on
the FPGA interface is between five to seven clock cycles of the reference clock (FPGA_SYSCLK).
The A1 and A2 bytes can also be intentionally corrupted for testing by the A1/A2 error insert control register
(0x3000D, 0x3000E). Only the last A1 and first A2 are corrupted. When A1/A2 corruption detection is set for a par-
ticular channel, the A1/A2 values in the corrupted A1/A2 value registers are sent for the number of frames defined
in the corrupted A1/A2 frame count register (0x3000C). When the corrupted A1/A2 frame count register is set to
0x00, A1/A2 corruption will continue until the A1/A2 error insert register is cleared.
The ORT8850 device only has one control register to set the A1/A2 bytes as well as the number of frames of cor-
ruption. To insert the corrupted A1/A2 each channel has an enable A1/A2 insert register. When the per channel
error insert register bit is set, the A1/A2 values are corrupted for the number specified in the number of frames to
corrupt. To insert errors again, the per channel error insert register bit must be cleared, and set again.
It is also possible to not insert the A1/A2 framing bytes using the per channel register bit “disable A1/A2 insert.”
B1 Processing
In the transmit direction a bit interleaved parity (BIP-8) error check set for even parity over all the bits of an STS-1
frame B1 is defined for the first STS-1 in an STS-12 only, the B1 calculation block computes a BIP-8 code, using
even parity over all bits of the previous STS-12 frame after scrambling and is inserted in the B1 byte of the current
STS-12 frame before scrambling.
Per-bit B1 corruption is controlled by the force BIP-8 corruption register (0x3000F). For any bit set in this register,
the corresponding bit in the calculated BIP-8 is inverted before insertion into the B1 byte position. Each stream has
an independent fault insert register that enables the inversion of the B1 bytes. B1 bytes in all other STS- 1s in the
stream are filled with zeros.
It is also possible to not insert the B1 byte using the per channel register bit "disable B1 insert."
A1
B1
D1
H1
B2
D4
D7
D10
S1
A1
D1
H1
B2
D4
D7
D10
S1
Regenerated bytes.
Bytes optionally inserted from TOH serial port data or transparently forwarded from parallel input port
Bytes transparently forwarded from parallel input port
Bytes transparently forwarded from parallel input port
0
A1
D1
H1
B2
D4
D7
D10
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
D10
A1
D1
H1
B2
D4
D7
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
A1
D1
H1
B2
D4
D7
D10
S1
0
D11
A2
E1
D2
H2
K1
D5
D8
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2
D2
H2
K1
D5
D8
D11
M0
E1
33
A2
D2
H2
K1
D5
D8
D11
M0
E1
D11
A2
E1
D2
H2
K1
D5
D8
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2
E1
D2
H2
K1
D5
D8
D11
M0
D3
H3
K2
D6
D9
D12
J0
F1
E2
ORCA ORT8850 Data Sheet
D3
H3
K2
D6
D9
D12
J0
F1
E2
D12
J0
F1
D3
H3
K2
D6
D9
E2
F1
D3
H3
K2
D6
D9
D12
E2
J0
D3
H3
K2
D6
D9
D12
E2
J0
F1
D3
H3
K2
D6
D9
D12
E2
J0
F1
D3
H3
K2
D6
D9
D12
J0
F1
E2
D3
H3
K2
D6
D9
D12
J0
F1
E2
D12
J0
F1
D3
H3
K2
D6
D9
E2
D12
J0
F1
D3
H3
K2
D6
D9
E2
F1
D3
H3
K2
D6
D9
D12
E2
J0
D3
H3
K2
D6
D9
D12
E2
J0
F1