ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 46

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
phases (i.e., received and system) are determined. This latch point is then stable unless the relative framing
changes and the received H byte times collide with the system F1 or E2 times, in which case the latch point would
be switched to the collision-free byte time.
There is no restriction on how many or how often increments and decrements are processed. Any received incre-
ment or decrement is immediately passed to the generator for implementation regardless of when the last pointer
adjustment was made. The responsibility for meeting the SONET criteria for maximum frequency of pointer adjust-
ments is left to an upstream pointer processor.
Receive Bypass Options
Not all of the blocks in the receive direction are required to be used. The following bypass options are valid in the
receive (backplane → FPGA) direction:
• STM Pointer Mover bypass:
• STM Pointer Mover and Alignment FIFO bypass:
Figure 26. Pointer Mover and Alignment FIFO Bypass Timing
Table 14 shows the register settings to enable the bypass modes.
Table 14. Register Settings for Bypass Mode
0x3000C
0x30020
0x30038
0x30050
0x30068
0x30080
0x30098
0x300B0
0x300C8
Register Address
– In this mode, data from the alignment FIFOs is transferred to the FPGA logic. All channels are synchronous
– When the pointer mover is used, the FPGA logic provides the frame pulse on the LINE_FP (recall: there is
– In this mode, data from the framer block is transferred to the FPGA logic. All channels supply data and frame
to the FPGA_SYSCLK signals driven to the FPGA logic, as is also the case when the pointer mover is not
bypassed. During bypass SPE, C1J1, and data parity signals are not valid. When the pointer mover is
bypassed, eight frame pulses (DOUTxx_FP) from aligned channels are provided by the embedded core to
the FPGA.
only one LINE_FP just like there is only one SYS_FP) signal essential for the Pointer Mover to move the
data. The FPGA gets eight channels of SONET data with the A1 byte position of each channel of the TOH
arbitrarily offset from the LINE_FP. The DOUTxx_FP signals are not valid when the pointer mover is used.
pulses synchronous with their individual recovered clock (CDR_CLK_xx) per channel. During bypass, SPE,
C1J1, and data parity signals are not valid. Additionally, no serial TOH_OUT_xx data and frame pulse sig-
nals will be available. The DOUTxx_FP signals are aligned with the A1 byte position of each channel, as
shown in Figure 26.
0x04
0x07
0x07
0x07
0x07
0x07
0x07
0x07
0x07
Value
DOUTxx_FP
CDR_CLK_xx
DOUTxx
Turn off the SONET scrambler/descrambler
Channel AA in functional mode
Channel AB in functional mode
Channel AC in functional mode
Channel AD in functional mode
Channel BA in functional mode
Channel BB in functional mode
Channel BC in functional mode
Channel BD in functional mode
46
First A1 Byte
Description
ORCA ORT8850 Data Sheet