ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 17

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
STM Macrocells - Overview
The Synchronous Transport Module (STM) portion of the embedded core consists of two quads, STM A and B. The
STM macrocells provide transmitter and receiver logic blocks on a per SERDES basis channel and are located in
the data path between the FPGA interface and the HSI macrocell. The STM macrocells' main functions are framing
and aligning data into standard STS-N frames as well as providing a 1's density through scrambling/descrambling.
Figure 7. STM Macrocell Partitioning
Transmit STM Macrocell Logic - Overview
In the transmit direction (FPGA interface to the backplane), each STM macrocell will receive frame aligned streams
of STS-12 data (maximum of four streams) from the FPGA logic. The transmitter receive data interface is in a par-
allel 8-bit format. A common frame pulse for all 8 channels is provided as an input from the FPGA logic to the trans-
mit SONET block.
On each frame pulse the A1/A2 frame alignment bytes are inserted into the data stream and will overwrite any data
in this location of the frame. TOH data can be optionally inserted into the transmitted SONET frame. The SONET
frame is then optionally scrambled and sent to the HSI macrocell.
TOH data can be inserted into the transmit data stream in two ways; transparently or by inserting serial TOH data
from a TOH serial interface signal in the FPGA logic. In the transparent mode, the SPE and TOH data received on
parallel input bus is transferred, unaltered, to the serial LVDS output. However, B1 byte of STS-1 is always replaced
with a new calculated value (the 11 bytes following B1 are replaced with all zeros). Likewise, in serial and transport
mode A1 and A2 bytes of all STS-1s are always regenerated. In the TOH serial insertion mode the SPE bytes are
transferred unaltered from the input parallel bus to the serial LVDS output. TOH bytes, however, are received from
the FPGA logic through the serial input port and are inserted in the STS- 12 frame before being sent to the LVDS
FPGA
Logic
FPGA_SYSCLK
DOUTAC[7:0]
DOUTAD[7:0]
DOUTBC[7:0]
DOUTBD[7:0]
DOUTAA[7:0]
DOUTAB[7:0]
DOUTBA[7:0]
DOUTBB[7:0]
DINAC[7:0]
DINAD[7:0]
DINBC[7:0]
DINBD[7:0]
DINAA[7:0]
DINAB[7:0]
DINBA[7:0]
DINBB[7:0]
SYS_FP
Common Signals
STM Macrocell
Channel AC
Channel AD
Channel BC
Channel BD
Channel AA
Channel AB
Channel BA
Channel BB
Quad B
Quad A
17
RX Serial DataAA
RX Serial DataAB
RX Serial DataAC
RX Serial DataAD
RX Serial DataBA
RX Serial DataBB
RX Serial DataBC
RX Serial DataBD
TX Serial DataAA
TX Serial DataAB
TX Serial DataAC
TX Serial DataAD
TX Serial DataBA
TX Serial DataBB
TX Serial DataBC
TX Serial DataBD
System Clock
ORCA ORT8850 Data Sheet
I/O DEMUX
Buffers
LVDS
and
RXDxx_W_[P:N]
RXDxx_P_[P:N]
TXDxx_P_[P:N]
Note: xx = AA, ...
TXDxx_W_[P:N]
SYS_CLK_[P:N]