ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 20

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ORCA ORT8850 Data Sheet
Pointer Mover Performance Monitoring: There is Pointer Mover performance monitoring in the Receiver section.
Alarm Indication Signals (AIS-P) and elastic store overflows are reported. AIS-P is implemented as a per STS-1
alarm bit. Elastic store overflow will cause an alarm bit to be set on a per STS-1 basis.
FIFO Aligner Monitoring: There is monitoring of the FIFO aligner operating point, and upon deviating from the nom-
inal operating point of the FIFO by more than user programmable threshold values (min and max threshold values),
an alarm bit is set. Threshold values are defined per device; alarm flags are per channel.
Frame Offset Monitoring: There is monitoring of the frame offset between all enabled channels (disabled channels
do not interfere with the monitoring). Monitoring is performed continuously. Upon exceeding the maximum allowed
frame offset (18 bytes) between all enabled channels, an alarm bit is set.
Error Insertion
A1/A2 Error Insert: There is a Frame Error inject feature in the transmitter section, allowing the user to replace
framing bytes A1/A2 (only last A1 byte and first A2 byte) with a selectable A1/A2 byte value for a selectable number
of consecutive frames. The number of consecutive frames to alter is specified by a 4-bit field, while A1/A2 value is
specified by two 8-bit fields. The error insert feature is on a per channel basis, A1/ A2 values and 4-bit frame count
value are on a per device basis.
B1 Error Insert: There is a B1 error insert feature in the transmitter section, allowing the user to insert errors on
user selectable bits in the B1 byte. Errors are created by simply inverting bit values. Bits to invert are specified
through an 8-bit control. To insert an error, software will first set the bits in the "transmitter B1 error insert mask".
Then, on a per channel basis software will write a one to the "B1 error insert command". The insertion circuitry per-
forms a rising edge detect on the bit, and will issue a corruption signal for the next frame, for one frame only. This
feature is on a per channel basis.
TOH Serial Output Port Parity Error Insert: There is a Parity error inject feature, in the receive section, allowing the
user to invert the parity bit of each serial output port. This feature inserts a single error. This feature is on a per
channel basis.
Parallel Output Bus Parity Error Insert: There is a Parity error inject feature, in the receive section, allowing the user
to invert parity lines (DOUTxx_PAR) associated with each output parallel busses (DOUTxx[7:0]). This feature
inserts a single error. This feature is on a per channel basis. This feature supports both 'even' and 'odd' parities.
Loopback
There are two types of loopback that can be utilized inside the embedded ASIC core of the ORT8850, near end
loopback and far end (line side) loopback. Both of these loopbacks are controlled by control registers inside the
ORT8850 core, which are accessible from the system bus and the MicroProcessor Interface (MPI). In both loop-
back modes, all channels are placed with a single control. The data paths in the two loopback modes are shown in
Figure 8.
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