ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 40

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
condition. It is also possible during operation for the channel to go into OOF. This may occur due to the removal of
either the frame pulse or the cable. If this is the case, AND is is part of a multi-channel alignment group, the realign-
ment procedure must be re-executed once the channel goes back into frame.
When a channel goes from the OOF state to the In-Frame state the OOF alarm bit is set per channel. The OOF
alarm bit is a per channel bit contained in the channel alarm register. It takes the receiver at least 4 full SONET
frames for the state machine to declare the In-Frame state. When the OOF bit is high the channel is in OOF. When
the OOF bit changes to a ‘0’ then the channel is back in frame and the realignment procedure should be executed.
Table 11 lists the register values to set up the ORT8850 for alignment FIFO sync realignment. The order is specific.
The values are given from the PowerPC point of view. If using the MPI to write data to the ORT8850, the value
given in the table is the value that should be used. If using the UMI of the system bus, the data value would need to
be byte flipped. The following setup procedures should be followed after the enabled channels have a valid frame
pulse, and are in the Frame state:
Table 11. Alignment FIFO Synch Realignment
RX Serial TOH Processing
Transport overhead is extracted from the receive data stream by the TOH extract block. The incoming data gets
loaded into a 36-byte shift register on the system clock domain. This, in turn, is clocked onto the TOH clock domain
at the start of the SPE time, where it can be clocked out.
The TOH processor is responsible for serializing all received TOH bytes of each channel through that channel's
corresponding serial TOH data port. The TOH serial ports are synchronized to the TOH clock (the same clock that
is being used by the serial ports on the transmitter side). This free-running TOH clock is provided to the core by
external circuitry and operates at a minimum frequency of 25 MHz and a maximum frequency of 77.76 MHz. Data
is transferred over serial links in a bursty fashion as controlled by the RX TOH clock enable signal, and is common
0x30020, bit 6
0x30038, bit 6
0x30050, bit 6
0x30068, bit 6
0x30080, bit 6
0x30098, bit 6
0x300B0, bit 6
0x300C8, bit 6
Wait for 4 SONET Frames (~500µs)
0x30017, specific bits
0x30018, specific bits
Wait for Another 4 SONET Frames (~500µs)
0x30017, specific bits
0x30018, specific bits
0x30020, bit 6
0x30038, bit 6
0x30050, bit 6
0x30068, bit 6
0x30080, bit 6
0x30098, bit 6
0x300B0, bit 6
0x300C8, bit 6
Register Address
Value (Binary)
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
Force AIS-L in all channels of the group to be synchronized.
Issue FIFO realignment commands.
Clear FIFO alignment command register bits written in previous steps.
Release AIS-L in all channels of the group to allow normal data flow through the
reveiver.
40
Description
ORCA ORT8850 Data Sheet