ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 28

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
• A1 and A2 framing bits are inserted (errored bits may optionally be inserted)
• The bit interleaved parity bit (B1) for the previously transmitted frame is inserted
• The data is scrambled using the standard STS-12 polynomial (optional)
• A parallel to serial conversion is performed on the data
• The serial data is broadcast to the work and protect LVDS buffers
These processing steps are described in more detail in the following sections. A block diagram of the transmit path
logic is shown in Figure 12. All processing except the parallel to serial conversion is optional. If all processing except
the SERDES is deselected, the device is said to be operating in the "bypass" mode.
Figure 12. Basic Logic Blocks, Transmit Path, Single Channel
Parity Checking
Parity error checking is implemented on each of the four parallel input buses on each STM quad (A & B) on a per
channel basis. "Even" or "Odd" parity can be selected by setting a control register bit. Upon detection of an error,
an alarm bit in a status register is set.
There is also even parity error checking on each of the four TOH serial input ports on a per channel basis. Upon
detection of an error, an alarm bit in a status register is set.
TOH Byte Modification
The transport overhead bytes of the SONET frame can be used for in-band configuration, service, and manage-
ment since it is carried along the same channel as data. In the ORT8850 in-band signaling can be efficiently uti-
lized, since the total cost of overhead is only 3.3%. TOH data can be inserted into the transmit data stream in one
of two ways, the Transparent Insertion mode and the Serial TOH Insertion mode. The overhead bytes in an STS-1
header are shown in Figure 13. (The path overhead bytes are in the SPE.)
TX_TOH_CK_EN
FPGA_SYSCLK
xx=[AA, AB,…BD]
Note:
DINxx [7:0]
DINxx _PAR
TOH_CLK
FPGA
Logic
TOH_Inxx
SYS_FP
8
Check
Parity
7 channels
Odd or Even
(from control
To other
Convert
Parallel
Serial
register)
TOH
To
Insert
(opt.)
TOH
Insert
A1A2
Error
(from control
A1A2
Insert
(opt.)
SONET Logic
registers)
Insert
Error
B1
Insert
(opt.)
B1
Prev.
Hold
B1
Repeater
STS 3)
Logic Common to Both Quads
7 channels
(for
To other
Calc.
28
B1
Embedded Core
Scrambler
(optional)
7 channels
To other
77.78 MHz
622 MHz
Convert
Parallel
Serial
PLL
To
ORCA ORT8850 Data Sheet
And LVDS
I/O MUXs
Buffers
LVDS
LVDS
LVDS
Buffer
Buffer
Buffer
2
2
2
SYS_CLK_[P:N]
TXDxx_W_[P:N]
TXDxx_P_[P:N]
Backplane
Links
Serial