ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 82

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ort8850

Manufacturer Part Number
ort8850
Description
Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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Table 35. ORT8850H Pins That Are Unused in ORT8850L
Users should avoid using these pins if they plan to migrate their ORT8850H design to an ORT8850L.
Package Pinouts
Table 36 provides the package pin and pin function for the ORT8850 FPSC and packages. The bond pad name is
identified in the PIO nomenclature used in the ispLEVER design editor. The Bank column provides information as
to which output voltage level bank the given pin is in. The Group column provides information as to the group of
pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-
ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then
the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
BGA Ball Bonds
AM14
AN14
AK10
AK11
AD5
AG1
AM9
AN9
AA2
AC4
AP4
D11
E13
W4
M5
K4
R5
Y4
T5
82
ORT8850H PIOs
PB10A
PB11A
PB12A
PB19A
PB20A
PT12A
PT11A
PL11A
PL13A
PL20A
PL21A
PL27A
PL28A
PL29A
PL35A
PL37A
PL38A
PB3A
PB9A
ORCA ORT8850 Data Sheet

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